target/arm: Enable FEAT_FGWTE3 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260806172709.333300-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 6, 2026 at 10:27 UTC
9b3e7f881b63415344018b8ef9077e47c8ccea50
2 files changed
+2
docs/system/arm/emulation.rst
+1
@@ -78,6 +78,7 @@ the following architecture extensions:
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- FEAT_FAMINMAX (Floating-point maximum and minimum absolute value instructions)
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- FEAT_FCMA (Floating-point complex number instructions)
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- FEAT_FGT (Fine-Grained Traps)
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+- FEAT_FGWTE3 (Fine-Grained Write Trap EL3)
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- FEAT_FHM (Floating-point half-precision multiplication instructions)
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- FEAT_FP (Floating Point extensions)
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- FEAT_FP16 (Half-precision floating-point data processing)
target/arm/tcg/cpu64.c
+1
@@ -1466,6 +1466,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
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t = GET_IDREG(isar, ID_AA64MMFR4);
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t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */
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+ t = FIELD_DP64(t, ID_AA64MMFR4, FGWTE3, 1); /* v9.4: FEAT_FGWTE3 */
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SET_IDREG(isar, ID_AA64MMFR4, t);
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t = GET_IDREG(isar, ID_AA64ZFR0);