hw/i3c: Split DesignWare I3C out of Aspeed I3C
The Aspeed I3C IP block is technically an Aspeed IP block that manages 6 DW I3C controllers. To help reflect this better and to make it easier for other SoCs to use the DW I3C model, we'll split out the DW portion from the Aspeed portion. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Feb 25, 2026 at 02:12 UTC
9b3eb0e2db0287b474451b3a7c9c1539f3fea173
8 files changed
+250
-194
hw/arm/Kconfig
+1
@@ -546,6 +546,7 @@ config ASPEED_SOC
546
select FTGMAC100
547
select I2C
548
select I3C
549
+ select DW_I3C
550
select DPS310
551
select PCA9552
552
select PCA9554
hw/i3c/Kconfig
+3
@@ -1,2 +1,5 @@
1
config I3C
2
bool
3
+
4
+config DW_I3C
5
+ bool
hw/i3c/aspeed_i3c.c
+3
-178
@@ -2,6 +2,7 @@
2
* ASPEED I3C Controller
3
*
4
* Copyright (C) 2021 ASPEED Technology Inc.
5
+ * Copyright (C) 2025 Google, LLC.
6
*
7
* This code is licensed under the GPL version 2 or later. See
8
* the COPYING file in the top-level directory.
@@ -43,162 +44,6 @@ REG32(I3C6_REG1, 0x64)
44
FIELD(I3C6_REG1, I2C_MODE, 0, 1)
45
FIELD(I3C6_REG1, SA_EN, 15, 1)
46
46
-/* I3C Device Registers */
47
-REG32(DEVICE_CTRL, 0x00)
48
-REG32(DEVICE_ADDR, 0x04)
49
-REG32(HW_CAPABILITY, 0x08)
50
-REG32(COMMAND_QUEUE_PORT, 0x0c)
51
-REG32(RESPONSE_QUEUE_PORT, 0x10)
52
-REG32(RX_TX_DATA_PORT, 0x14)
53
-REG32(IBI_QUEUE_STATUS, 0x18)
54
-REG32(IBI_QUEUE_DATA, 0x18)
55
-REG32(QUEUE_THLD_CTRL, 0x1c)
56
-REG32(DATA_BUFFER_THLD_CTRL, 0x20)
57
-REG32(IBI_QUEUE_CTRL, 0x24)
58
-REG32(IBI_MR_REQ_REJECT, 0x2c)
59
-REG32(IBI_SIR_REQ_REJECT, 0x30)
60
-REG32(RESET_CTRL, 0x34)
61
-REG32(SLV_EVENT_CTRL, 0x38)
62
-REG32(INTR_STATUS, 0x3c)
63
-REG32(INTR_STATUS_EN, 0x40)
64
-REG32(INTR_SIGNAL_EN, 0x44)
65
-REG32(INTR_FORCE, 0x48)
66
-REG32(QUEUE_STATUS_LEVEL, 0x4c)
67
-REG32(DATA_BUFFER_STATUS_LEVEL, 0x50)
68
-REG32(PRESENT_STATE, 0x54)
69
-REG32(CCC_DEVICE_STATUS, 0x58)
70
-REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c)
71
- FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16)
72
- FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16)
73
-REG32(DEV_CHAR_TABLE_POINTER, 0x60)
74
-REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c)
75
-REG32(SLV_MIPI_PID_VALUE, 0x70)
76
-REG32(SLV_PID_VALUE, 0x74)
77
-REG32(SLV_CHAR_CTRL, 0x78)
78
-REG32(SLV_MAX_LEN, 0x7c)
79
-REG32(MAX_READ_TURNAROUND, 0x80)
80
-REG32(MAX_DATA_SPEED, 0x84)
81
-REG32(SLV_DEBUG_STATUS, 0x88)
82
-REG32(SLV_INTR_REQ, 0x8c)
83
-REG32(DEVICE_CTRL_EXTENDED, 0xb0)
84
-REG32(SCL_I3C_OD_TIMING, 0xb4)
85
-REG32(SCL_I3C_PP_TIMING, 0xb8)
86
-REG32(SCL_I2C_FM_TIMING, 0xbc)
87
-REG32(SCL_I2C_FMP_TIMING, 0xc0)
88
-REG32(SCL_EXT_LCNT_TIMING, 0xc8)
89
-REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc)
90
-REG32(BUS_FREE_TIMING, 0xd4)
91
-REG32(BUS_IDLE_TIMING, 0xd8)
92
-REG32(I3C_VER_ID, 0xe0)
93
-REG32(I3C_VER_TYPE, 0xe4)
94
-REG32(EXTENDED_CAPABILITY, 0xe8)
95
-REG32(SLAVE_CONFIG, 0xec)
96
-
97
-static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
98
- [R_HW_CAPABILITY] = 0x000e00bf,
99
- [R_QUEUE_THLD_CTRL] = 0x01000101,
100
- [R_I3C_VER_ID] = 0x3130302a,
101
- [R_I3C_VER_TYPE] = 0x6c633033,
102
- [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280,
103
- [R_DEV_CHAR_TABLE_POINTER] = 0x00020200,
104
- [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
105
- [R_SLV_MAX_LEN] = 0x00ff00ff,
106
-};
107
-
108
-static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
109
- unsigned size)
110
-{
111
- AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque);
112
- uint32_t addr = offset >> 2;
113
- uint64_t value;
114
-
115
- switch (addr) {
116
- case R_COMMAND_QUEUE_PORT:
117
- value = 0;
118
- break;
119
- default:
120
- value = s->regs[addr];
121
- break;
122
- }
123
-
124
- trace_aspeed_i3c_device_read(s->id, offset, value);
125
-
126
- return value;
127
-}
128
-
129
-static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
130
- uint64_t value, unsigned size)
131
-{
132
- AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque);
133
- uint32_t addr = offset >> 2;
134
-
135
- trace_aspeed_i3c_device_write(s->id, offset, value);
136
-
137
- switch (addr) {
138
- case R_HW_CAPABILITY:
139
- case R_RESPONSE_QUEUE_PORT:
140
- case R_IBI_QUEUE_DATA:
141
- case R_QUEUE_STATUS_LEVEL:
142
- case R_PRESENT_STATE:
143
- case R_CCC_DEVICE_STATUS:
144
- case R_DEVICE_ADDR_TABLE_POINTER:
145
- case R_VENDOR_SPECIFIC_REG_POINTER:
146
- case R_SLV_CHAR_CTRL:
147
- case R_SLV_MAX_LEN:
148
- case R_MAX_READ_TURNAROUND:
149
- case R_I3C_VER_ID:
150
- case R_I3C_VER_TYPE:
151
- case R_EXTENDED_CAPABILITY:
152
- qemu_log_mask(LOG_GUEST_ERROR,
153
- "%s: write to readonly register[0x%02" HWADDR_PRIx
154
- "] = 0x%08" PRIx64 "\n",
155
- __func__, offset, value);
156
- break;
157
- case R_RX_TX_DATA_PORT:
158
- break;
159
- case R_RESET_CTRL:
160
- break;
161
- default:
162
- s->regs[addr] = value;
163
- break;
164
- }
165
-}
166
-
167
-static const VMStateDescription aspeed_i3c_device_vmstate = {
168
- .name = TYPE_ASPEED_I3C,
169
- .version_id = 1,
170
- .minimum_version_id = 1,
171
- .fields = (const VMStateField[]){
172
- VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS),
173
- VMSTATE_END_OF_LIST(),
174
- }
175
-};
176
-
177
-static const MemoryRegionOps aspeed_i3c_device_ops = {
178
- .read = aspeed_i3c_device_read,
179
- .write = aspeed_i3c_device_write,
180
- .endianness = DEVICE_LITTLE_ENDIAN,
181
-};
182
-
183
-static void aspeed_i3c_device_reset(DeviceState *dev)
184
-{
185
- AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev);
186
-
187
- memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs));
188
-}
189
-
190
-static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp)
191
-{
192
- AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev);
193
- g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d",
194
- s->id);
195
-
196
- sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
197
-
198
- memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops,
199
- s, name, ASPEED_I3C_DEVICE_NR_REGS << 2);
200
-}
201
-
47
static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size)
48
{
49
AspeedI3CState *s = ASPEED_I3C(opaque);
@@ -275,7 +120,7 @@ static void aspeed_i3c_instance_init(Object *obj)
120
121
for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) {
122
object_initialize_child(obj, "device[*]", &s->devices[i],
278
- TYPE_ASPEED_I3C_DEVICE);
123
+ TYPE_DW_I3C);
124
}
125
}
126
@@ -323,20 +168,6 @@ static void aspeed_i3c_realize(DeviceState *dev, Error **errp)
168
169
}
170
326
-static const Property aspeed_i3c_device_properties[] = {
327
- DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0),
328
-};
329
-
330
-static void aspeed_i3c_device_class_init(ObjectClass *klass, const void *data)
331
-{
332
- DeviceClass *dc = DEVICE_CLASS(klass);
333
-
334
- dc->desc = "Aspeed I3C Device";
335
- dc->realize = aspeed_i3c_device_realize;
336
- device_class_set_legacy_reset(dc, aspeed_i3c_device_reset);
337
- device_class_set_props(dc, aspeed_i3c_device_properties);
338
-}
339
-
171
static const VMStateDescription vmstate_aspeed_i3c = {
172
.name = TYPE_ASPEED_I3C,
173
.version_id = 1,
@@ -344,7 +175,7 @@ static const VMStateDescription vmstate_aspeed_i3c = {
175
.fields = (const VMStateField[]) {
176
VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS),
177
VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1,
347
- aspeed_i3c_device_vmstate, AspeedI3CDevice),
178
+ vmstate_dw_i3c, DWI3C),
179
VMSTATE_END_OF_LIST(),
180
}
181
};
@@ -367,12 +198,6 @@ static const TypeInfo aspeed_i3c_types[] = {
198
.instance_size = sizeof(AspeedI3CState),
199
.class_init = aspeed_i3c_class_init,
200
},
370
- {
371
- .name = TYPE_ASPEED_I3C_DEVICE,
372
- .parent = TYPE_SYS_BUS_DEVICE,
373
- .instance_size = sizeof(AspeedI3CDevice),
374
- .class_init = aspeed_i3c_device_class_init,
375
- },
201
};
202
203
DEFINE_TYPES(aspeed_i3c_types)
hw/i3c/dw-i3c.c
new
+202
@@ -0,0 +1,202 @@
1
+/*
2
+ * DesignWare I3C Controller
3
+ *
4
+ * Copyright (C) 2021 ASPEED Technology Inc.
5
+ * Copyright (C) 2025 Google, LLC
6
+ *
7
+ * SPDX-License-Identifier: GPL-2.0-or-later
8
+ */
9
+
10
+#include "qemu/osdep.h"
11
+#include "qemu/log.h"
12
+#include "qemu/error-report.h"
13
+#include "hw/i3c/i3c.h"
14
+#include "hw/i3c/dw-i3c.h"
15
+#include "hw/core/registerfields.h"
16
+#include "hw/core/qdev-properties.h"
17
+#include "qapi/error.h"
18
+#include "migration/vmstate.h"
19
+#include "trace.h"
20
+
21
+REG32(DEVICE_CTRL, 0x00)
22
+REG32(DEVICE_ADDR, 0x04)
23
+REG32(HW_CAPABILITY, 0x08)
24
+REG32(COMMAND_QUEUE_PORT, 0x0c)
25
+REG32(RESPONSE_QUEUE_PORT, 0x10)
26
+REG32(RX_TX_DATA_PORT, 0x14)
27
+REG32(IBI_QUEUE_STATUS, 0x18)
28
+REG32(IBI_QUEUE_DATA, 0x18)
29
+REG32(QUEUE_THLD_CTRL, 0x1c)
30
+REG32(DATA_BUFFER_THLD_CTRL, 0x20)
31
+REG32(IBI_QUEUE_CTRL, 0x24)
32
+REG32(IBI_MR_REQ_REJECT, 0x2c)
33
+REG32(IBI_SIR_REQ_REJECT, 0x30)
34
+REG32(RESET_CTRL, 0x34)
35
+REG32(SLV_EVENT_CTRL, 0x38)
36
+REG32(INTR_STATUS, 0x3c)
37
+REG32(INTR_STATUS_EN, 0x40)
38
+REG32(INTR_SIGNAL_EN, 0x44)
39
+REG32(INTR_FORCE, 0x48)
40
+REG32(QUEUE_STATUS_LEVEL, 0x4c)
41
+REG32(DATA_BUFFER_STATUS_LEVEL, 0x50)
42
+REG32(PRESENT_STATE, 0x54)
43
+REG32(CCC_DEVICE_STATUS, 0x58)
44
+REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c)
45
+ FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16)
46
+ FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16)
47
+REG32(DEV_CHAR_TABLE_POINTER, 0x60)
48
+REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c)
49
+REG32(SLV_MIPI_PID_VALUE, 0x70)
50
+REG32(SLV_PID_VALUE, 0x74)
51
+REG32(SLV_CHAR_CTRL, 0x78)
52
+REG32(SLV_MAX_LEN, 0x7c)
53
+REG32(MAX_READ_TURNAROUND, 0x80)
54
+REG32(MAX_DATA_SPEED, 0x84)
55
+REG32(SLV_DEBUG_STATUS, 0x88)
56
+REG32(SLV_INTR_REQ, 0x8c)
57
+REG32(DEVICE_CTRL_EXTENDED, 0xb0)
58
+REG32(SCL_I3C_OD_TIMING, 0xb4)
59
+REG32(SCL_I3C_PP_TIMING, 0xb8)
60
+REG32(SCL_I2C_FM_TIMING, 0xbc)
61
+REG32(SCL_I2C_FMP_TIMING, 0xc0)
62
+REG32(SCL_EXT_LCNT_TIMING, 0xc8)
63
+REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc)
64
+REG32(BUS_FREE_TIMING, 0xd4)
65
+REG32(BUS_IDLE_TIMING, 0xd8)
66
+REG32(I3C_VER_ID, 0xe0)
67
+REG32(I3C_VER_TYPE, 0xe4)
68
+REG32(EXTENDED_CAPABILITY, 0xe8)
69
+REG32(SLAVE_CONFIG, 0xec)
70
+
71
+static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {
72
+ [R_HW_CAPABILITY] = 0x000e00bf,
73
+ [R_QUEUE_THLD_CTRL] = 0x01000101,
74
+ [R_I3C_VER_ID] = 0x3130302a,
75
+ [R_I3C_VER_TYPE] = 0x6c633033,
76
+ [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280,
77
+ [R_DEV_CHAR_TABLE_POINTER] = 0x00020200,
78
+ [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
79
+ [R_SLV_MAX_LEN] = 0x00ff00ff,
80
+};
81
+
82
+static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
83
+{
84
+ DWI3C *s = DW_I3C(opaque);
85
+ uint32_t addr = offset >> 2;
86
+ uint64_t value;
87
+
88
+ switch (addr) {
89
+ case R_COMMAND_QUEUE_PORT:
90
+ value = 0;
91
+ break;
92
+ default:
93
+ value = s->regs[addr];
94
+ break;
95
+ }
96
+
97
+ trace_dw_i3c_read(s->id, offset, value);
98
+
99
+ return value;
100
+}
101
+
102
+static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,
103
+ unsigned size)
104
+{
105
+ DWI3C *s = DW_I3C(opaque);
106
+ uint32_t addr = offset >> 2;
107
+
108
+ trace_dw_i3c_write(s->id, offset, value);
109
+
110
+ switch (addr) {
111
+ case R_HW_CAPABILITY:
112
+ case R_RESPONSE_QUEUE_PORT:
113
+ case R_IBI_QUEUE_DATA:
114
+ case R_QUEUE_STATUS_LEVEL:
115
+ case R_PRESENT_STATE:
116
+ case R_CCC_DEVICE_STATUS:
117
+ case R_DEVICE_ADDR_TABLE_POINTER:
118
+ case R_VENDOR_SPECIFIC_REG_POINTER:
119
+ case R_SLV_CHAR_CTRL:
120
+ case R_SLV_MAX_LEN:
121
+ case R_MAX_READ_TURNAROUND:
122
+ case R_I3C_VER_ID:
123
+ case R_I3C_VER_TYPE:
124
+ case R_EXTENDED_CAPABILITY:
125
+ qemu_log_mask(LOG_GUEST_ERROR,
126
+ "%s: write to readonly register[0x%02" HWADDR_PRIx
127
+ "] = 0x%08" PRIx64 "\n",
128
+ __func__, offset, value);
129
+ break;
130
+ case R_RX_TX_DATA_PORT:
131
+ break;
132
+ case R_RESET_CTRL:
133
+ break;
134
+ default:
135
+ s->regs[addr] = value;
136
+ break;
137
+ }
138
+}
139
+
140
+const VMStateDescription vmstate_dw_i3c = {
141
+ .name = TYPE_DW_I3C,
142
+ .version_id = 1,
143
+ .minimum_version_id = 1,
144
+ .fields = (VMStateField[]){
145
+ VMSTATE_UINT32_ARRAY(regs, DWI3C, DW_I3C_NR_REGS),
146
+ VMSTATE_END_OF_LIST(),
147
+ }
148
+};
149
+
150
+static const MemoryRegionOps dw_i3c_ops = {
151
+ .read = dw_i3c_read,
152
+ .write = dw_i3c_write,
153
+ .endianness = DEVICE_LITTLE_ENDIAN,
154
+};
155
+
156
+static void dw_i3c_reset_enter(Object *obj, ResetType type)
157
+{
158
+ DWI3C *s = DW_I3C(obj);
159
+
160
+ memcpy(s->regs, dw_i3c_resets, sizeof(s->regs));
161
+}
162
+
163
+static void dw_i3c_realize(DeviceState *dev, Error **errp)
164
+{
165
+ DWI3C *s = DW_I3C(dev);
166
+ g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->id);
167
+
168
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
169
+
170
+ memory_region_init_io(&s->mr, OBJECT(s), &dw_i3c_ops, s, name,
171
+ DW_I3C_NR_REGS << 2);
172
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr);
173
+}
174
+
175
+static const Property dw_i3c_properties[] = {
176
+ DEFINE_PROP_UINT8("device-id", DWI3C, id, 0),
177
+};
178
+
179
+static void dw_i3c_class_init(ObjectClass *klass, const void *data)
180
+{
181
+ DeviceClass *dc = DEVICE_CLASS(klass);
182
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
183
+
184
+ rc->phases.enter = dw_i3c_reset_enter;
185
+
186
+ dc->desc = "DesignWare I3C Controller";
187
+ dc->realize = dw_i3c_realize;
188
+ dc->vmsd = &vmstate_dw_i3c;
189
+ device_class_set_props(dc, dw_i3c_properties);
190
+}
191
+
192
+static const TypeInfo dw_i3c_types[] = {
193
+ {
194
+ .name = TYPE_DW_I3C,
195
+ .parent = TYPE_SYS_BUS_DEVICE,
196
+ .instance_size = sizeof(DWI3C),
197
+ .class_init = dw_i3c_class_init,
198
+ },
199
+};
200
+
201
+DEFINE_TYPES(dw_i3c_types)
202
+
hw/i3c/meson.build
+1
@@ -1,4 +1,5 @@
1
i3c_ss = ss.source_set()
2
i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c'))
3
i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c'))
4
+i3c_ss.add(when: 'CONFIG_DW_I3C', if_true: files('dw-i3c.c'))
5
system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss)
hw/i3c/trace-events
+4
-2
@@ -3,8 +3,10 @@
3
# aspeed_i3c.c
4
aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64
5
aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64
6
-aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
7
-aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
6
+
7
+# dw-i3c,c
8
+dw_i3c_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
9
+dw_i3c_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
10
11
# core.c
12
i3c_target_event(uint8_t address, uint8_t event) "I3C target 0x%" PRIx8 " event 0x%" PRIx8
include/hw/i3c/aspeed_i3c.h
+3
-14
@@ -10,27 +10,15 @@
10
#ifndef ASPEED_I3C_H
11
#define ASPEED_I3C_H
12
13
+#include "hw/i3c/dw-i3c.h"
14
#include "hw/core/sysbus.h"
15
16
#define TYPE_ASPEED_I3C "aspeed.i3c"
16
-#define TYPE_ASPEED_I3C_DEVICE "aspeed.i3c.device"
17
OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C)
18
19
#define ASPEED_I3C_NR_REGS (0x70 >> 2)
20
-#define ASPEED_I3C_DEVICE_NR_REGS (0x300 >> 2)
20
#define ASPEED_I3C_NR_DEVICES 6
21
23
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE)
24
-struct AspeedI3CDevice {
25
- SysBusDevice parent_obj;
26
-
27
- MemoryRegion mr;
28
- qemu_irq irq;
29
-
30
- uint8_t id;
31
- uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS];
32
-};
33
-
22
struct AspeedI3CState {
23
SysBusDevice parent_obj;
24
@@ -39,6 +27,7 @@ struct AspeedI3CState {
27
qemu_irq irq;
28
29
uint32_t regs[ASPEED_I3C_NR_REGS];
42
- AspeedI3CDevice devices[ASPEED_I3C_NR_DEVICES];
30
+ DWI3C devices[ASPEED_I3C_NR_DEVICES];
31
+ uint8_t id;
32
};
33
#endif /* ASPEED_I3C_H */
include/hw/i3c/dw-i3c.h
new
+33
@@ -0,0 +1,33 @@
1
+/*
2
+ * DesignWare I3C Controller
3
+ *
4
+ * Copyright (C) 2021 ASPEED Technology Inc.
5
+ * Copyright (C) 2025 Google, LLC.
6
+ *
7
+ * SPDX-License-Identifier: GPL-2.0-or-later
8
+ */
9
+
10
+#ifndef DW_I3C_H
11
+#define DW_I3C_H
12
+
13
+#include "hw/core/sysbus.h"
14
+
15
+#define TYPE_DW_I3C "dw.i3c"
16
+OBJECT_DECLARE_SIMPLE_TYPE(DWI3C, DW_I3C)
17
+
18
+#define DW_I3C_NR_REGS (0x300 >> 2)
19
+
20
+struct DWI3C {
21
+ SysBusDevice parent_obj;
22
+
23
+ MemoryRegion mr;
24
+ qemu_irq irq;
25
+
26
+ uint8_t id;
27
+ uint32_t regs[DW_I3C_NR_REGS];
28
+};
29
+
30
+/* Extern for other controllers that use DesignWare I3C. */
31
+extern const VMStateDescription vmstate_dw_i3c;
32
+
33
+#endif /* DW_I3C_H */