target/loongarch: Use sys_state in csr_helper.c when accessing CSR registers
When accessing CSR registers in file csr_helper.c, use sys_state rather than env. There is no function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com> Tested-by: Song Gao <gaosong@loongson.cn> Message-ID: <20260605082552.175336-9-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Bibo Mao committed
Jun 5, 2026 at 16:25 UTC
9c93f9e5ed9e8001d1e65b0d7ce75e82a6ff7bab
1 file changed
+32
-23
target/loongarch/tcg/csr_helper.c
+32
-23
@@ -20,7 +20,8 @@
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target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
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{
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- int64_t old_v = env->CSR_STLBPS;
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+ CPUSysState *sys = env_sys(env);
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+ int64_t old_v = sys->CSR_STLBPS;
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/*
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* The real hardware only supports the min tlb_ps is 12
@@ -33,7 +34,7 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
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} else {
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/* Only update PS field, reserved bit keeps zero */
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val = FIELD_DP64(val, CSR_STLBPS, RESERVE, 0);
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- env->CSR_STLBPS = val;
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+ sys->CSR_STLBPS = val;
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}
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return old_v;
@@ -42,17 +43,18 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
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target_ulong helper_csrrd_pgd(CPULoongArchState *env)
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{
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int64_t v;
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+ CPUSysState *sys = env_sys(env);
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- if (env->CSR_TLBRERA & 0x1) {
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- v = env->CSR_TLBRBADV;
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+ if (sys->CSR_TLBRERA & 0x1) {
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+ v = sys->CSR_TLBRBADV;
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} else {
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- v = env->CSR_BADV;
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+ v = sys->CSR_BADV;
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}
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if ((v >> 63) & 0x1) {
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- v = env->CSR_PGDH;
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+ v = sys->CSR_PGDH;
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} else {
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- v = env->CSR_PGDL;
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+ v = sys->CSR_PGDL;
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}
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return v;
@@ -61,10 +63,11 @@ target_ulong helper_csrrd_pgd(CPULoongArchState *env)
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target_ulong helper_csrrd_cpuid(CPULoongArchState *env)
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{
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LoongArchCPU *lac = env_archcpu(env);
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+ CPUSysState *sys = env_sys(env);
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- env->CSR_CPUID = CPU(lac)->cpu_index;
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+ sys->CSR_CPUID = CPU(lac)->cpu_index;
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- return env->CSR_CPUID;
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+ return sys->CSR_CPUID;
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}
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target_ulong helper_csrrd_tval(CPULoongArchState *env)
@@ -77,16 +80,17 @@ target_ulong helper_csrrd_tval(CPULoongArchState *env)
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target_ulong helper_csrrd_msgir(CPULoongArchState *env)
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{
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int irq, new;
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+ CPUSysState *sys = env_sys(env);
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- irq = find_first_bit((unsigned long *)env->CSR_MSGIS, 256);
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+ irq = find_first_bit((unsigned long *)sys->CSR_MSGIS, 256);
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if (irq < 256) {
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- clear_bit(irq, (unsigned long *)env->CSR_MSGIS);
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- new = find_first_bit((unsigned long *)env->CSR_MSGIS, 256);
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+ clear_bit(irq, (unsigned long *)sys->CSR_MSGIS);
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+ new = find_first_bit((unsigned long *)sys->CSR_MSGIS, 256);
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if (new < 256) {
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return irq;
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}
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- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0);
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+ sys->CSR_ESTAT = FIELD_DP64(sys->CSR_ESTAT, CSR_ESTAT, MSGINT, 0);
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} else {
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/* bit 31 set 1 for no invalid irq */
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irq = BIT(31);
@@ -97,21 +101,23 @@ target_ulong helper_csrrd_msgir(CPULoongArchState *env)
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target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
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{
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- int64_t old_v = env->CSR_ESTAT;
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+ CPUSysState *sys = env_sys(env);
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+ int64_t old_v = sys->CSR_ESTAT;
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/* Only IS[1:0] can be written */
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- env->CSR_ESTAT = deposit64(env->CSR_ESTAT, 0, 2, val);
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+ sys->CSR_ESTAT = deposit64(sys->CSR_ESTAT, 0, 2, val);
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return old_v;
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}
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target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val)
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{
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- int64_t old_v = env->CSR_ASID;
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+ CPUSysState *sys = env_sys(env);
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+ int64_t old_v = sys->CSR_ASID;
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/* Only ASID filed of CSR_ASID can be written */
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- env->CSR_ASID = deposit64(env->CSR_ASID, 0, 10, val);
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- if (old_v != env->CSR_ASID) {
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+ sys->CSR_ASID = deposit64(sys->CSR_ASID, 0, 10, val);
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+ if (old_v != sys->CSR_ASID) {
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tlb_flush(env_cpu(env));
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}
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return old_v;
@@ -120,7 +126,8 @@ target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val)
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target_ulong helper_csrwr_tcfg(CPULoongArchState *env, target_ulong val)
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{
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LoongArchCPU *cpu = env_archcpu(env);
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- int64_t old_v = env->CSR_TCFG;
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+ CPUSysState *sys = env_sys(env);
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+ int64_t old_v = sys->CSR_TCFG;
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cpu_loongarch_store_constant_timer_config(cpu, val);
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@@ -143,7 +150,8 @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env, target_ulong val)
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target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)
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{
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uint8_t shift, ptbase;
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- int64_t old_v = env->CSR_PWCL;
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+ CPUSysState *sys = env_sys(env);
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+ int64_t old_v = sys->CSR_PWCL;
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/*
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* The real hardware only supports 64bit PTE width now, 128bit or others
@@ -160,14 +168,15 @@ target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attempted set ptbase 2^%d\n", ptbase);
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}
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- env->CSR_PWCL = val;
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+ sys->CSR_PWCL = val;
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return old_v;
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}
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target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val)
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{
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uint8_t has_ptw;
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- int64_t old_v = env->CSR_PWCH;
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+ CPUSysState *sys = env_sys(env);
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+ int64_t old_v = sys->CSR_PWCH;
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val = FIELD_DP64(val, CSR_PWCH, RESERVE, 0);
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has_ptw = FIELD_EX32(env->cpucfg[2], CPUCFG2, HPTW);
@@ -175,6 +184,6 @@ target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val)
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val = FIELD_DP64(val, CSR_PWCH, HPTW_EN, 0);
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}
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- env->CSR_PWCH = val;
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+ sys->CSR_PWCH = val;
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return old_v;
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}