target/arm: Implement FMOP4A (widening, 2-way, FP8 to FP16)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260702204314.79224-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jul 2, 2026 at 13:43 UTC
9f0194dd12fb8d06aece8219635713c544275892
5 files changed
+27
target/arm/cpu-features.h
+5
@@ -1827,6 +1827,11 @@ static inline bool isar_feature_aa64_sme_mop4_f8f32(const ARMISARegisters *id)
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return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f8f32(id);
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}
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+static inline bool isar_feature_aa64_sme_mop4_f8f16(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f8f16(id);
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+}
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+
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
target/arm/tcg/fp8_helper.c
+16
@@ -989,3 +989,19 @@ void HELPER(sme_fmop4a_sb)(void *vza, void *vzn, void *vzm,
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FP8MulContext ctx = fp8_mul_start(env, -1);
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sme_mop4(vza, vzn, vzm, &ctx, desc, sizeof(float32), inner_fmop4a_sb);
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}
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+
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+static void inner_fmop4a_hb(void *vd, void *vn, void *vm, void *vinfo)
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+{
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+ float16 *d = vd;
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+ uint16_t *n = vn, *m = vm;
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+ FP8MulContext *ctx = vinfo;
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+
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+ *d = f8dotadd_h(*n, *m, 2, *d, ctx);
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+}
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+
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+void HELPER(sme_fmop4a_hb)(void *vza, void *vzn, void *vzm,
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+ CPUArchState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
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+ sme_mop4(vza, vzn, vzm, &ctx, desc, sizeof(float16), inner_fmop4a_hb);
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+}
target/arm/tcg/helper-fp8-defs.h
+1
@@ -46,3 +46,4 @@ DEF_HELPER_FLAGS_5(sme_fvdot_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
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DEF_HELPER_FLAGS_5(sme_fvdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_5(sme_fmop4a_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
49
+DEF_HELPER_FLAGS_5(sme_fmop4a_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
target/arm/tcg/sme.decode
+3
@@ -1101,6 +1101,8 @@ LUTI4_s_4b 1100 0000 1001 101 1 00 00 00 ....0 zd:5 \
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@mop4_o3 .... .... ... m:1 .... .... .. n:1 ... . s:1 . zad:3 \
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&mop4 zm=%mop4_zm zn=%mop4_zn
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+@mop4_o1_s0 .... .... ... m:1 .... .... .. n:1 ... . .... zad:1 \
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+ &mop4 zm=%mop4_zm zn=%mop4_zn s=0
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@mop4_o2_s0 .... .... ... m:1 .... .... .. n:1 ... . ... zad:2 \
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&mop4 zm=%mop4_zm zn=%mop4_zn s=0
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@@ -1113,3 +1115,4 @@ BFMOP4_sh 1000 0001 000. ...0 0000 00.. ..0. 00.. @mop4_o2
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FMOP4_sh 1000 0001 001. ...0 0000 00.. ..0. 00.. @mop4_o2
1116
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FMOP4A_sb 1000 0000 001. ...0 0000 00.. ..00 00.. @mop4_o2_s0
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+FMOP4A_hb 1000 0000 001. ...0 0000 00.. ..00 100. @mop4_o1_s0
target/arm/tcg/translate-sme.c
+2
@@ -2090,3 +2090,5 @@ static bool do_mop4_fp8(DisasContext *s, arg_mop4 *a, MemOp esz,
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TRANS_FEAT(FMOP4A_sb, aa64_sme_mop4_f8f32,
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do_mop4_fp8, a, MO_32, gen_helper_sme_fmop4a_sb)
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+TRANS_FEAT(FMOP4A_hb, aa64_sme_mop4_f8f16,
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+ do_mop4_fp8, a, MO_16, gen_helper_sme_fmop4a_hb)