target/riscv: mask vxrm csrw write to the low 2 bits

Citing the RISC-V specification: "The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the least-significant bits (vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as zeros." QEMU wrote full value into env->vxrm causing read of upper bits too. Used existing macros for bit-masking. Previous had a hard-coded value. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3470 Signed-off-by: Abhigyan Kumar <314abh@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260530102100.78150-1-314abh@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>