hw/riscv: Register generic riscv[32|64] QOM interfaces
Defines generic 32- and 64-bit riscv machine interfaces for machines to implement. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Anton Johansson committed
Apr 30, 2025 at 13:34 UTC
a045f6a8e819dcc0e80d13fbd1cedf60c85cef79
2 files changed
+29
include/hw/riscv/machines-qom.h
new
+20
@@ -0,0 +1,20 @@
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+/*
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+ * QOM type definitions for riscv32 / riscv64 machines
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+ *
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+ * Copyright (c) rev.ng Labs Srl.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#ifndef HW_RISCV_MACHINES_QOM_H
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+#define HW_RISCV_MACHINES_QOM_H
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+
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+#include "hw/core/boards.h"
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+
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+#define TYPE_TARGET_RISCV32_MACHINE \
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+ "target-info-riscv32-machine"
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+
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+#define TYPE_TARGET_RISCV64_MACHINE \
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+ "target-info-riscv64-machine"
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+
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+#endif
target-info-qom.c
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@@ -13,6 +13,7 @@
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#include "qemu/target-info-init.h"
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#include "qemu/target-info-qom.h"
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#include "hw/arm/machines-qom.h"
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+#include "hw/riscv/machines-qom.h"
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static const TypeInfo target_info_types[] = {
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{
@@ -23,6 +24,14 @@ static const TypeInfo target_info_types[] = {
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.name = TYPE_TARGET_AARCH64_MACHINE,
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.parent = TYPE_INTERFACE,
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},
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+ {
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+ .name = TYPE_TARGET_RISCV32_MACHINE,
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+ .parent = TYPE_INTERFACE,
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+ },
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+ {
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+ .name = TYPE_TARGET_RISCV64_MACHINE,
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+ .parent = TYPE_INTERFACE,
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+ },
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};
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DEFINE_TYPES(target_info_types)