hw/riscv/riscv_hart.c isolate tcg only bits
riscv_cpu_register_csr_qtest_callback(), vcsr_call() and csr_qtest_callback() are all TCG only and are not available in --disable-tcg builds. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-ID: <20260703180538.3346781-19-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 3, 2026 at 15:05 UTC
a0b0643890becbbd3c2bfbf004a929438cfd58d6
1 file changed
+5
-3
hw/riscv/riscv_hart.c
+5
-3
@@ -61,7 +61,7 @@ static void riscv_harts_cpu_reset(void *opaque)
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cpu_reset(CPU(cpu));
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}
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-#ifndef CONFIG_USER_ONLY
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+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
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{
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RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num));
@@ -151,8 +151,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp)
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s->harts = g_new0(RISCVCPU, s->num_harts);
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-#ifndef CONFIG_USER_ONLY
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- riscv_cpu_register_csr_qtest_callback();
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+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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+ if (qtest_enabled()) {
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+ riscv_cpu_register_csr_qtest_callback();
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+ }
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#endif
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for (n = 0; n < s->num_harts; n++) {