target/arm: Move aa32_max_features to tcg/cpu32.c
The function is unused without TCG, so move. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-id: 20260812204435.295067-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 18, 2026 at 10:39 UTC
a2c25ce4138926c8ab44738263c35e8c329b9961
2 files changed
+96
-96
target/arm/cpu-max.c
-96
@@ -85,102 +85,6 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enabled)
85
define_cortex_a72_a57_a53_cp_reginfo(cpu);
86
}
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88
-/* Share AArch32 -cpu max features with AArch64. */
89
-void aa32_max_features(ARMCPU *cpu)
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-{
91
- uint32_t t;
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- ARMISARegisters *isar = &cpu->isar;
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-
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- /* Add additional features supported by QEMU */
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- t = GET_IDREG(isar, ID_ISAR5);
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- t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
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- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
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- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
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- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
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- t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
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- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
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- SET_IDREG(isar, ID_ISAR5, t);
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-
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- t = GET_IDREG(isar, ID_ISAR6);
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- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
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- t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
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- t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
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- t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
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- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
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- t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
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- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
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- SET_IDREG(isar, ID_ISAR6, t);
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-
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- t = cpu->isar.mvfr1;
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- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
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- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
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- cpu->isar.mvfr1 = t;
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-
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- t = cpu->isar.mvfr2;
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- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
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- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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- cpu->isar.mvfr2 = t;
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-
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- FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
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-
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- t = GET_IDREG(isar, ID_MMFR4);
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- t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
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- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
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- t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */
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- SET_IDREG(isar, ID_MMFR4, t);
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-
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- FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
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-
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- t = GET_IDREG(isar, ID_PFR0);
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- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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- t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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- t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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- SET_IDREG(isar, ID_PFR0, t);
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-
142
- t = GET_IDREG(isar, ID_PFR2);
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- t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
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- t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
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- SET_IDREG(isar, ID_PFR2, t);
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-
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- t = GET_IDREG(isar, ID_DFR0);
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- t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
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- SET_IDREG(isar, ID_DFR0, t);
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-
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- /* Debug ID registers. */
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-
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- /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
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- t = 0x00008000;
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- t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
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- t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
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- t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
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- t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
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- t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
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- t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
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- cpu->isar.dbgdidr = t;
164
-
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- t = 0;
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- t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
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- t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
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- t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
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- t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
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- t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
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- t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
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- t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
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- t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
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- cpu->isar.dbgdevid = t;
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-
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- /* Bits[31:4] are RES0. */
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- t = 0;
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- t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
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- cpu->isar.dbgdevid1 = t;
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-
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- FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
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-}
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-
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/*
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* -cpu max: a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
target/arm/tcg/cpu32.c
+96
@@ -749,6 +749,102 @@ type_init(arm_tcg_cpu_register_types)
749
750
#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
751
752
+/* Share AArch32 -cpu max features with AArch64. */
753
+void aa32_max_features(ARMCPU *cpu)
754
+{
755
+ uint32_t t;
756
+ ARMISARegisters *isar = &cpu->isar;
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+
758
+ /* Add additional features supported by QEMU */
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+ t = GET_IDREG(isar, ID_ISAR5);
760
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
761
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
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+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
763
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
764
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
765
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
766
+ SET_IDREG(isar, ID_ISAR5, t);
767
+
768
+ t = GET_IDREG(isar, ID_ISAR6);
769
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
770
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
771
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
772
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
773
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
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+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
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+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
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+ SET_IDREG(isar, ID_ISAR6, t);
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+
778
+ t = cpu->isar.mvfr1;
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+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
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+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
781
+ cpu->isar.mvfr1 = t;
782
+
783
+ t = cpu->isar.mvfr2;
784
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
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+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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+ cpu->isar.mvfr2 = t;
787
+
788
+ FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
789
+
790
+ t = GET_IDREG(isar, ID_MMFR4);
791
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
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+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
795
+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */
796
+ SET_IDREG(isar, ID_MMFR4, t);
797
+
798
+ FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
799
+
800
+ t = GET_IDREG(isar, ID_PFR0);
801
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
802
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
803
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
804
+ SET_IDREG(isar, ID_PFR0, t);
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+
806
+ t = GET_IDREG(isar, ID_PFR2);
807
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
808
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
809
+ SET_IDREG(isar, ID_PFR2, t);
810
+
811
+ t = GET_IDREG(isar, ID_DFR0);
812
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
813
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
814
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
815
+ SET_IDREG(isar, ID_DFR0, t);
816
+
817
+ /* Debug ID registers. */
818
+
819
+ /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
820
+ t = 0x00008000;
821
+ t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
822
+ t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
823
+ t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
824
+ t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
825
+ t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
826
+ t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
827
+ cpu->isar.dbgdidr = t;
828
+
829
+ t = 0;
830
+ t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
831
+ t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
832
+ t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
833
+ t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
834
+ t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
835
+ t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
836
+ t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
837
+ t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
838
+ cpu->isar.dbgdevid = t;
839
+
840
+ /* Bits[31:4] are RES0. */
841
+ t = 0;
842
+ t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
843
+ cpu->isar.dbgdevid1 = t;
844
+
845
+ FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
846
+}
847
+
848
void aarch32_max_tcg_init(ARMCPU *cpu)
849
{
850
aarch64_aa32_a57_init(cpu, false);