target/ppc: Move isync instruction to decodetree
Moving the following instructions to decodetree specification : isync The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Ojaswin Mujoo <ojaswin@linux.ibm.com> Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-14-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Ojaswin Mujoo committed
Aug 27, 2026 at 18:59 UTC
a3521772cbaaf8b5a06605c8288b044fbfb0c878
3 files changed
+18
-15
target/ppc/insn32.decode
+1
@@ -1470,6 +1470,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 -
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@X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync
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SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync
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EIEIO 011111 ----- ----- ----- 1101010110 -
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+ISYNC 010011 ----- ----- ----- 0010010110 -
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# Condition Register Field Instruction
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target/ppc/translate.c
-15
@@ -2727,20 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
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static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
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#endif
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-/* isync */
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-static void gen_isync(DisasContext *ctx)
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-{
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- /*
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- * We need to check for a pending TLB flush. This can only happen in
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- * kernel mode however so check MSR_PR
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- */
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- if (!ctx->pr) {
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- gen_check_tlb_flush(ctx, false);
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- }
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- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
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- ctx->base.is_jmp = DISAS_EXIT_UPDATE;
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-}
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-
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/* wait */
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static void gen_wait(DisasContext *ctx)
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{
@@ -5364,7 +5350,6 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
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GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
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GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
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GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
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-GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
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/* ISA v3.0 changed the extended opcode from 62 to 30 */
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GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
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GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300),
target/ppc/translate/storage-ctrl-impl.c.inc
+17
@@ -155,6 +155,23 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
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return true;
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}
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+static bool trans_ISYNC(DisasContext *ctx, arg_ISYNC *a)
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+{
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+ REQUIRE_INSNS_FLAGS(ctx, MEM);
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+
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+ /*
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+ * We need to check for a pending TLB flush. This can only happen in
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+ * kernel mode however so check MSR_PR
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+ */
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+ if (!ctx->pr) {
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+ gen_check_tlb_flush(ctx, false);
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+ }
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+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
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+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
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+
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+ return true;
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+}
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+
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static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a)
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{
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REQUIRE_64BIT(ctx);