@samitouri / QOSamiQemu / commits / a39d7662cd

hw/i3c/mock-i3c-target: Simplify GETMRL byte extraction logic

The GETMRL handling logic extracted MSB/LSB bytes from s->cfg.buf_size using a mask-and-shift expression: (buf_size & (0xff00 >> (offset * 8))) >> (8 - (offset * 8)) While functionally correct, the expression is difficult to read and obscures the intent, which is simply to return a 16-bit value in MSB-first order. Replace the mask/shift formula with explicit MSB/LSB extraction: offset == 0 -> buf_size >> 8 offset == 1 -> buf_size & 0xff This makes the code clearer and easier to review without altering behavior or data ordering. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260303013322.1297499-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>

Jamin Lin committed Mar 3, 2026 at 01:33 UTC a39d7662cd1d6bf50b277955dff0d26592a12de9

1 file changed +6 -3

hw/i3c/mock-i3c-target.c

+6 -3

@@ -146,9 +146,12 @@ static int mock_i3c_target_handle_ccc_read(I3CTarget *i3c, uint8_t *data,

146 if (s->ccc_byte_offset >= 2) {

147 break;

148 }

149 - data[s->ccc_byte_offset] = (s->cfg.buf_size &

150 - (0xff00 >> (s->ccc_byte_offset * 8))) >>

151 - (8 - (s->ccc_byte_offset * 8));

149 + if (s->ccc_byte_offset == 0) {

150 + data[s->ccc_byte_offset] = (uint8_t)(s->cfg.buf_size >> 8);

151 + } else {

152 + data[s->ccc_byte_offset] = (uint8_t)s->cfg.buf_size;

153 + }

154 +

155 s->ccc_byte_offset++;

156 *num_read = num_to_read;

157 }