hw/arm: ax3000-soc: Enable Cadence GPIO controllers
Enable 8 Cadence GPIO controllers into Axiado AX3000 SoC Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-id: 20260713073033.3883619-9-kchiu@axiado.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Kuan-Jui Chiu committed
Aug 11, 2026 at 20:14 UTC
a4256760c0e0a123569be2e99d8749f00b812c1d
3 files changed
+52
hw/arm/Kconfig
+1
@@ -731,6 +731,7 @@ config AXIADO_SOC
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select ARM_GIC
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select CADENCE # UART
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select AXIADO_CLK
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+ select CADENCE_GPIO
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select AXIADO_SDHCI
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select UNIMP
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hw/arm/ax3000-soc.c
+30
@@ -36,6 +36,11 @@ static void ax3000_init(Object *obj)
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object_initialize_child(obj, "clk", &s->ax3000_clk, TYPE_AX3000_CLK);
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object_initialize_child(obj, "sdhci0", &s->sdhci0, TYPE_AXIADO_SDHCI);
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+
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+ for (int i = 0; i < AX3000_NUM_GPIOS; i++) {
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+ g_autofree char *name = g_strdup_printf("gpio%d", i);
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+ object_initialize_child(obj, name, &s->gpio[i], TYPE_CADENCE_GPIO);
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+ }
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}
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static void ax3000_realize(DeviceState *dev, Error **errp)
@@ -187,6 +192,31 @@ static void ax3000_realize(DeviceState *dev, Error **errp)
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&error_fatal);
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qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal);
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}
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+
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+ /* GPIOs */
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+ const struct {
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+ hwaddr addr;
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+ unsigned int irq;
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+ } gpio_table[] = {
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+ { AX3000_GPIO0_BASE, AX3000_GPIO0_IRQ },
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+ { AX3000_GPIO1_BASE, AX3000_GPIO1_IRQ },
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+ { AX3000_GPIO2_BASE, AX3000_GPIO2_IRQ },
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+ { AX3000_GPIO3_BASE, AX3000_GPIO3_IRQ },
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+ { AX3000_GPIO4_BASE, AX3000_GPIO4_IRQ },
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+ { AX3000_GPIO5_BASE, AX3000_GPIO5_IRQ },
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+ { AX3000_GPIO6_BASE, AX3000_GPIO6_IRQ },
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+ { AX3000_GPIO7_BASE, AX3000_GPIO7_IRQ }
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+ };
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+
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+ for (int i = 0; i < AX3000_NUM_GPIOS; i++) {
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
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+ return;
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+ }
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+
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+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
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+ qdev_get_gpio_in(gic_dev, gpio_table[i].irq));
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+ }
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}
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static void ax3000_class_init(ObjectClass *oc, const void *data)
include/hw/arm/ax3000-soc.h
+21
@@ -13,6 +13,7 @@
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/char/cadence_uart.h"
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#include "hw/misc/axiado_clk.h"
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+#include "hw/gpio/cadence_gpio.h"
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#include "hw/sd/axiado_sdhci.h"
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#include "hw/core/sysbus.h"
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#include "qemu/units.h"
@@ -38,6 +39,15 @@ OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX3000_SOC)
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#define AX3000_SDHCI0_BASE 0x86000000
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#define AX3000_EMMC_PHY_BASE 0x80801C00
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+#define AX3000_GPIO0_BASE 0x80500000
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+#define AX3000_GPIO1_BASE 0x80580000
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+#define AX3000_GPIO2_BASE 0x80600000
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+#define AX3000_GPIO3_BASE 0x80680000
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+#define AX3000_GPIO4_BASE 0x80700000
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+#define AX3000_GPIO5_BASE 0x80780000
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+#define AX3000_GPIO6_BASE 0x80800000
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+#define AX3000_GPIO7_BASE 0x80880000
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+
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#define AX3000_TIMER_CTRL 0x8A020000
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#define AX3000_PLL_BASE 0x80000000
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@@ -46,6 +56,7 @@ enum Ax3000Configuration {
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AX3000_NUM_IRQS = 224,
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AX3000_NUM_BANKS = 2,
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AX3000_NUM_UARTS = 4,
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+ AX3000_NUM_GPIOS = 8,
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};
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typedef struct Ax3000SoCState {
@@ -56,6 +67,7 @@ typedef struct Ax3000SoCState {
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MemoryRegion dram[AX3000_NUM_BANKS];
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Ax3000ClkState ax3000_clk;
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CadenceUARTState uart[AX3000_NUM_UARTS];
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+ CadenceGPIOState gpio[AX3000_NUM_GPIOS];
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AxiadoSDHCIState sdhci0;
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} Ax3000SoCState;
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@@ -72,6 +84,15 @@ enum Ax3000Irqs {
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AX3000_UART3_IRQ = 170,
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AX3000_SDHCI0_IRQ = 123,
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+
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+ AX3000_GPIO0_IRQ = 183,
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+ AX3000_GPIO1_IRQ = 184,
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+ AX3000_GPIO2_IRQ = 185,
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+ AX3000_GPIO3_IRQ = 186,
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+ AX3000_GPIO4_IRQ = 187,
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+ AX3000_GPIO5_IRQ = 188,
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+ AX3000_GPIO6_IRQ = 189,
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+ AX3000_GPIO7_IRQ = 190,
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};
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#endif /* AXIADO_AX3000_H */