@samitouri / QOSamiQemu / commits / a4a35544e4

target/riscv: Reject Svinval instructions in U-mode

The RISC-V privileged specification requires SFENCE.W.INVAL and SFENCE.INVAL.IR to raise an illegal instruction exception when executed in U-mode. Check the current privilege mode during translation and reject these instructions in U-mode, so they are reported as illegal instructions. Add a helper to reject these instructions in U-mode during translation. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3493 Suggested-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260522033145.17850-1-fritchleybohrer@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Zephyr Li committed May 22, 2026 at 11:31 UTC a4a35544e43220657f718a5d0be5ab49c6129000

1 file changed +12

target/riscv/insn_trans/trans_svinval.c.inc

+12

@@ -22,11 +22,19 @@

22 } \

23 } while (0)

25 +/* Test if priv level is M or S. */

26 +#define REQUIRE_PRIV_MS(ctx) do { \

27 + if (ctx->priv == PRV_U) { \

28 + return false; \

29 + } \

30 +} while (0)

31 +

32 static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)

33 {

34 REQUIRE_SVINVAL(ctx);

35 /* Do the same as sfence.vma currently */

36 REQUIRE_EXT(ctx, RVS);

37 + REQUIRE_PRIV_MS(ctx);

38 #ifndef CONFIG_USER_ONLY

39 decode_save_opc(ctx, 0);

40 gen_helper_tlb_flush(tcg_env);

@@ -39,6 +47,7 @@ static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)

47 {

48 REQUIRE_SVINVAL(ctx);

49 REQUIRE_EXT(ctx, RVS);

50 + REQUIRE_PRIV_MS(ctx);

51 /* Do nothing currently */

52 return true;

53 }

@@ -47,6 +56,7 @@ static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)

56 {

57 REQUIRE_SVINVAL(ctx);

58 REQUIRE_EXT(ctx, RVS);

59 + REQUIRE_PRIV_MS(ctx);

60 /* Do nothing currently */

61 return true;

62 }

@@ -56,6 +66,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)

66 REQUIRE_SVINVAL(ctx);

67 /* Do the same as hfence.vvma currently */

68 REQUIRE_EXT(ctx, RVH);

69 + REQUIRE_PRIV_MS(ctx);

70 #ifndef CONFIG_USER_ONLY

71 decode_save_opc(ctx, 0);

72 gen_helper_hyp_tlb_flush(tcg_env);

@@ -69,6 +80,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)

80 REQUIRE_SVINVAL(ctx);

81 /* Do the same as hfence.gvma currently */

82 REQUIRE_EXT(ctx, RVH);

83 + REQUIRE_PRIV_MS(ctx);

84 #ifndef CONFIG_USER_ONLY

85 decode_save_opc(ctx, 0);

86 gen_helper_hyp_gvma_tlb_flush(tcg_env);