target/arm: Rename sve unary predicated patterns
Add an "_m" suffix to indicate merging, in preparation for adding new predicated zeroing instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260604234852.573178-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 4, 2026 at 16:48 UTC
a57e761b71bea3d8cc2d691644f492b1c6c76b05
2 files changed
+166
-157
target/arm/tcg/sve.decode
+77
-77
@@ -392,24 +392,24 @@ LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
392
393
# SVE unary bit operations (predicated)
394
# Note esz != 0 for FABS and FNEG.
395
-CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
396
-CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
397
-CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
398
-CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
399
-NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
400
-FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
401
-FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
395
+CLS_m 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
396
+CLZ_m 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
397
+CNT_zpz_m 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
398
+CNOT_m 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
399
+NOT_zpz_m 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
400
+FABS_m 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
401
+FNEG_m 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
402
403
# SVE integer unary operations (predicated)
404
# Note esz > original size for extensions.
405
-ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
406
-NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
407
-SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
408
-UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
409
-SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
410
-UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
411
-SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
412
-UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
405
+ABS_m 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
406
+NEG_m 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
407
+SXTB_m 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
408
+UXTB_m 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
409
+SXTH_m 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
410
+UXTH_m 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
411
+SXTW_m 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
412
+UXTW_m 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
413
414
### SVE Floating Point Compare - Vectors Group
415
@@ -707,11 +707,11 @@ CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
707
708
# SVE reverse within elements
709
# Note esz >= operation size
710
-REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
711
-REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
712
-REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
713
-RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
714
-REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0
710
+REVB_m 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
711
+REVH_m 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
712
+REVW_m 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
713
+RBIT_m 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
714
+REVD_m 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0
715
716
# SVE vector splice (predicated, destructive)
717
SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
@@ -1184,59 +1184,59 @@ FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
1184
### SVE FP Unary Operations Predicated Group
1185
1186
# SVE floating-point convert precision
1187
-FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1188
-FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1189
-BFCVT 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1190
-FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1191
-FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1192
-FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1193
-FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
1187
+FCVT_sh_m 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1188
+FCVT_hs_m 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1189
+BFCVT_m 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1190
+FCVT_dh_m 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1191
+FCVT_hd_m 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1192
+FCVT_ds_m 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1193
+FCVT_sd_m 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
1194
1195
# SVE floating-point convert to integer
1196
-FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
1197
-FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
1198
-FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1199
-FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1200
-FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1201
-FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1202
-FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1203
-FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1204
-FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0
1205
-FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0
1206
-FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1207
-FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1208
-FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1209
-FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1196
+FCVTZS_hh_m 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
1197
+FCVTZU_hh_m 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
1198
+FCVTZS_hs_m 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1199
+FCVTZU_hs_m 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1200
+FCVTZS_hd_m 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1201
+FCVTZU_hd_m 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1202
+FCVTZS_ss_m 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1203
+FCVTZU_ss_m 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1204
+FCVTZS_ds_m 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0
1205
+FCVTZU_ds_m 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0
1206
+FCVTZS_sd_m 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1207
+FCVTZU_sd_m 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1208
+FCVTZS_dd_m 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1209
+FCVTZU_dd_m 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1210
1211
# SVE floating-point round to integral value
1212
-FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
1213
-FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
1214
-FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
1215
-FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
1216
-FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
1217
-FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
1218
-FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
1212
+FRINTN_m 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
1213
+FRINTP_m 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
1214
+FRINTM_m 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
1215
+FRINTZ_m 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
1216
+FRINTA_m 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
1217
+FRINTX_m 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
1218
+FRINTI_m 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
1219
1220
# SVE floating-point unary operations
1221
-FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
1222
-FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
1221
+FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
1222
+FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
1223
1224
# SVE integer convert to floating-point
1225
-SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
1226
-SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1227
-SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1228
-SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1229
-SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
1230
-SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1231
-SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1232
-
1233
-UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
1234
-UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1235
-UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1236
-UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1237
-UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
1238
-UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1239
-UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1225
+SCVTF_hh_m 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
1226
+SCVTF_sh_m 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1227
+SCVTF_dh_m 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1228
+SCVTF_ss_m 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1229
+SCVTF_sd_m 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
1230
+SCVTF_ds_m 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1231
+SCVTF_dd_m 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1232
+
1233
+UCVTF_hh_m 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
1234
+UCVTF_sh_m 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1235
+UCVTF_dh_m 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1236
+UCVTF_ss_m 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1237
+UCVTF_sd_m 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
1238
+UCVTF_ds_m 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1239
+UCVTF_dd_m 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1240
1241
### SVE Memory - 32-bit Gather and Unsized Contiguous Group
1242
@@ -1517,10 +1517,10 @@ UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn
1517
1518
### SVE2 integer unary operations (predicated)
1519
1520
-URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn
1521
-URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn
1522
-SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn
1523
-SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn
1520
+URECPE_m 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn
1521
+URSQRTE_m 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn
1522
+SQABS_m 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn
1523
+SQNEG_m 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn
1524
1525
### SVE2 saturating/rounding bitwise shift left (predicated)
1526
@@ -1847,16 +1847,16 @@ SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
1847
RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
1848
1849
### SVE2 floating-point convert precision odd elements
1850
-FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1851
-FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1852
-FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1853
-BFCVTNT 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1854
-FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1855
-FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1856
-FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
1850
+FCVTXNT_ds_m 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1851
+FCVTX_ds_m 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1852
+FCVTNT_sh_m 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1853
+BFCVTNT_m 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1854
+FCVTLT_hs_m 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1855
+FCVTNT_ds_m 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1856
+FCVTLT_sd_m 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
1857
1858
### SVE2 floating-point convert to integer
1859
-FLOGB 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz
1859
+FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz
1860
1861
### SVE2 floating-point multiply-add long (vectors)
1862
FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
target/arm/tcg/translate-sve.c
+89
-80
@@ -783,14 +783,14 @@ TRANS_FEAT(SEL_zpzz, aa64_sme_or_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg, a->e
783
}; \
784
TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0)
785
786
-DO_ZPZ(CLS, aa64_sme_or_sve, sve_cls)
787
-DO_ZPZ(CLZ, aa64_sme_or_sve, sve_clz)
788
-DO_ZPZ(CNT_zpz, aa64_sme_or_sve, sve_cnt_zpz)
789
-DO_ZPZ(CNOT, aa64_sme_or_sve, sve_cnot)
790
-DO_ZPZ(NOT_zpz, aa64_sme_or_sve, sve_not_zpz)
791
-DO_ZPZ(ABS, aa64_sme_or_sve, sve_abs)
792
-DO_ZPZ(NEG, aa64_sme_or_sve, sve_neg)
793
-DO_ZPZ(RBIT, aa64_sme_or_sve, sve_rbit)
786
+DO_ZPZ(CLS_m, aa64_sme_or_sve, sve_cls)
787
+DO_ZPZ(CLZ_m, aa64_sme_or_sve, sve_clz)
788
+DO_ZPZ(CNT_zpz_m, aa64_sme_or_sve, sve_cnt_zpz)
789
+DO_ZPZ(CNOT_m, aa64_sme_or_sve, sve_cnot)
790
+DO_ZPZ(NOT_zpz_m, aa64_sme_or_sve, sve_not_zpz)
791
+DO_ZPZ(ABS_m, aa64_sme_or_sve, sve_abs)
792
+DO_ZPZ(NEG_m, aa64_sme_or_sve, sve_neg)
793
+DO_ZPZ(RBIT_m, aa64_sme_or_sve, sve_rbit)
794
DO_ZPZ(ORQV, aa64_sme2p1_or_sve2p1, sve2p1_orqv)
795
DO_ZPZ(EORQV, aa64_sme2p1_or_sve2p1, sve2p1_eorqv)
796
DO_ZPZ(ANDQV, aa64_sme2p1_or_sve2p1, sve2p1_andqv)
@@ -803,7 +803,7 @@ static gen_helper_gvec_3 * const fabs_ah_fns[4] = {
803
NULL, gen_helper_sve_ah_fabs_h,
804
gen_helper_sve_ah_fabs_s, gen_helper_sve_ah_fabs_d,
805
};
806
-TRANS_FEAT(FABS, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
806
+TRANS_FEAT(FABS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
807
s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 0)
808
809
static gen_helper_gvec_3 * const fneg_fns[4] = {
@@ -814,34 +814,38 @@ static gen_helper_gvec_3 * const fneg_ah_fns[4] = {
814
NULL, gen_helper_sve_ah_fneg_h,
815
gen_helper_sve_ah_fneg_s, gen_helper_sve_ah_fneg_d,
816
};
817
-TRANS_FEAT(FNEG, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
817
+TRANS_FEAT(FNEG_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
818
s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 0)
819
820
static gen_helper_gvec_3 * const sxtb_fns[4] = {
821
NULL, gen_helper_sve_sxtb_h,
822
gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d,
823
};
824
-TRANS_FEAT(SXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0)
824
+TRANS_FEAT(SXTB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
825
+ sxtb_fns[a->esz], a, 0)
826
827
static gen_helper_gvec_3 * const uxtb_fns[4] = {
828
NULL, gen_helper_sve_uxtb_h,
829
gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d,
830
};
830
-TRANS_FEAT(UXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0)
831
+TRANS_FEAT(UXTB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
832
+ uxtb_fns[a->esz], a, 0)
833
834
static gen_helper_gvec_3 * const sxth_fns[4] = {
835
NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d
836
};
835
-TRANS_FEAT(SXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0)
837
+TRANS_FEAT(SXTH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
838
+ sxth_fns[a->esz], a, 0)
839
840
static gen_helper_gvec_3 * const uxth_fns[4] = {
841
NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d
842
};
840
-TRANS_FEAT(UXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0)
843
+TRANS_FEAT(UXTH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
844
+ uxth_fns[a->esz], a, 0)
845
842
-TRANS_FEAT(SXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
846
+TRANS_FEAT(SXTW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
847
a->esz == 3 ? gen_helper_sve_sxtw_d : NULL, a, 0)
844
-TRANS_FEAT(UXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
848
+TRANS_FEAT(UXTW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
849
a->esz == 3 ? gen_helper_sve_uxtw_d : NULL, a, 0)
850
851
static gen_helper_gvec_3 * const addqv_fns[4] = {
@@ -2984,17 +2988,19 @@ static gen_helper_gvec_3 * const revb_fns[4] = {
2988
NULL, gen_helper_sve_revb_h,
2989
gen_helper_sve_revb_s, gen_helper_sve_revb_d,
2990
};
2987
-TRANS_FEAT(REVB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0)
2991
+TRANS_FEAT(REVB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
2992
+ revb_fns[a->esz], a, 0)
2993
2994
static gen_helper_gvec_3 * const revh_fns[4] = {
2995
NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d,
2996
};
2992
-TRANS_FEAT(REVH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
2997
+TRANS_FEAT(REVH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
2998
+ revh_fns[a->esz], a, 0)
2999
2994
-TRANS_FEAT(REVW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
3000
+TRANS_FEAT(REVW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz,
3001
a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
3002
2997
-TRANS_FEAT(REVD, aa64_sme_or_sve2p1, gen_gvec_ool_arg_zpz,
3003
+TRANS_FEAT(REVD_m, aa64_sme_or_sve2p1, gen_gvec_ool_arg_zpz,
3004
gen_helper_sme_revd_q, a, 0)
3005
3006
TRANS_FEAT(SPLICE, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz,
@@ -4491,53 +4497,53 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sme_or_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz
4497
*** SVE Floating Point Unary Operations Predicated Group
4498
*/
4499
4494
-TRANS_FEAT(FCVT_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4500
+TRANS_FEAT(FCVT_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4501
gen_helper_sve_fcvt_sh, a, 0, FPST_A64)
4496
-TRANS_FEAT(FCVT_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4502
+TRANS_FEAT(FCVT_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4503
gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16)
4504
4499
-TRANS_FEAT(BFCVT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
4505
+TRANS_FEAT(BFCVT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
4506
gen_helper_sve_bfcvt, a, 0,
4507
s->fpcr_ah ? FPST_AH : FPST_A64)
4508
4503
-TRANS_FEAT(FCVT_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4509
+TRANS_FEAT(FCVT_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4510
gen_helper_sve_fcvt_dh, a, 0, FPST_A64)
4505
-TRANS_FEAT(FCVT_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4511
+TRANS_FEAT(FCVT_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4512
gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16)
4507
-TRANS_FEAT(FCVT_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4513
+TRANS_FEAT(FCVT_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4514
gen_helper_sve_fcvt_ds, a, 0, FPST_A64)
4509
-TRANS_FEAT(FCVT_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4515
+TRANS_FEAT(FCVT_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4516
gen_helper_sve_fcvt_sd, a, 0, FPST_A64)
4517
4512
-TRANS_FEAT(FCVTZS_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4518
+TRANS_FEAT(FCVTZS_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4519
gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16)
4514
-TRANS_FEAT(FCVTZU_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4520
+TRANS_FEAT(FCVTZU_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4521
gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16)
4516
-TRANS_FEAT(FCVTZS_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4522
+TRANS_FEAT(FCVTZS_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4523
gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16)
4518
-TRANS_FEAT(FCVTZU_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4524
+TRANS_FEAT(FCVTZU_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4525
gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16)
4520
-TRANS_FEAT(FCVTZS_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4526
+TRANS_FEAT(FCVTZS_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4527
gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16)
4522
-TRANS_FEAT(FCVTZU_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4528
+TRANS_FEAT(FCVTZU_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4529
gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16)
4530
4525
-TRANS_FEAT(FCVTZS_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4531
+TRANS_FEAT(FCVTZS_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4532
gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64)
4527
-TRANS_FEAT(FCVTZU_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4533
+TRANS_FEAT(FCVTZU_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4534
gen_helper_sve_fcvtzu_ss, a, 0, FPST_A64)
4529
-TRANS_FEAT(FCVTZS_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4535
+TRANS_FEAT(FCVTZS_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4536
gen_helper_sve_fcvtzs_sd, a, 0, FPST_A64)
4531
-TRANS_FEAT(FCVTZU_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4537
+TRANS_FEAT(FCVTZU_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4538
gen_helper_sve_fcvtzu_sd, a, 0, FPST_A64)
4533
-TRANS_FEAT(FCVTZS_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4539
+TRANS_FEAT(FCVTZS_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4540
gen_helper_sve_fcvtzs_ds, a, 0, FPST_A64)
4535
-TRANS_FEAT(FCVTZU_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4541
+TRANS_FEAT(FCVTZU_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4542
gen_helper_sve_fcvtzu_ds, a, 0, FPST_A64)
4543
4538
-TRANS_FEAT(FCVTZS_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4544
+TRANS_FEAT(FCVTZS_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4545
gen_helper_sve_fcvtzs_dd, a, 0, FPST_A64)
4540
-TRANS_FEAT(FCVTZU_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4546
+TRANS_FEAT(FCVTZU_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4547
gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64)
4548
4549
static gen_helper_gvec_3_ptr * const frint_fns[] = {
@@ -4546,8 +4552,9 @@ static gen_helper_gvec_3_ptr * const frint_fns[] = {
4552
gen_helper_sve_frint_s,
4553
gen_helper_sve_frint_d
4554
};
4549
-TRANS_FEAT(FRINTI, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz],
4550
- a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
4555
+TRANS_FEAT(FRINTI_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4556
+ frint_fns[a->esz], a, 0,
4557
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
4558
4559
static gen_helper_gvec_3_ptr * const frintx_fns[] = {
4560
NULL,
@@ -4555,8 +4562,9 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] = {
4562
gen_helper_sve_frintx_s,
4563
gen_helper_sve_frintx_d
4564
};
4558
-TRANS_FEAT(FRINTX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
4559
- a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
4565
+TRANS_FEAT(FRINTX_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4566
+ frintx_fns[a->esz], a, 0,
4567
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
4568
4569
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
4570
ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
@@ -4585,63 +4593,64 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
4593
return true;
4594
}
4595
4588
-TRANS_FEAT(FRINTN, aa64_sme_or_sve, do_frint_mode, a,
4596
+TRANS_FEAT(FRINTN_m, aa64_sme_or_sve, do_frint_mode, a,
4597
FPROUNDING_TIEEVEN, frint_fns[a->esz])
4590
-TRANS_FEAT(FRINTP, aa64_sme_or_sve, do_frint_mode, a,
4598
+TRANS_FEAT(FRINTP_m, aa64_sme_or_sve, do_frint_mode, a,
4599
FPROUNDING_POSINF, frint_fns[a->esz])
4592
-TRANS_FEAT(FRINTM, aa64_sme_or_sve, do_frint_mode, a,
4600
+TRANS_FEAT(FRINTM_m, aa64_sme_or_sve, do_frint_mode, a,
4601
FPROUNDING_NEGINF, frint_fns[a->esz])
4594
-TRANS_FEAT(FRINTZ, aa64_sme_or_sve, do_frint_mode, a,
4602
+TRANS_FEAT(FRINTZ_m, aa64_sme_or_sve, do_frint_mode, a,
4603
FPROUNDING_ZERO, frint_fns[a->esz])
4596
-TRANS_FEAT(FRINTA, aa64_sme_or_sve, do_frint_mode, a,
4604
+TRANS_FEAT(FRINTA_m, aa64_sme_or_sve, do_frint_mode, a,
4605
FPROUNDING_TIEAWAY, frint_fns[a->esz])
4606
4607
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
4608
NULL, gen_helper_sve_frecpx_h,
4609
gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,
4610
};
4603
-TRANS_FEAT(FRECPX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz],
4604
- a, 0, select_ah_fpst(s, a->esz))
4611
+TRANS_FEAT(FRECPX_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4612
+ frecpx_fns[a->esz], a, 0, select_ah_fpst(s, a->esz))
4613
4614
static gen_helper_gvec_3_ptr * const fsqrt_fns[] = {
4615
NULL, gen_helper_sve_fsqrt_h,
4616
gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d,
4617
};
4610
-TRANS_FEAT(FSQRT, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz],
4611
- a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
4618
+TRANS_FEAT(FSQRT_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4619
+ fsqrt_fns[a->esz], a, 0,
4620
+ a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
4621
4613
-TRANS_FEAT(SCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4622
+TRANS_FEAT(SCVTF_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4623
gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16)
4615
-TRANS_FEAT(SCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4624
+TRANS_FEAT(SCVTF_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4625
gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16)
4617
-TRANS_FEAT(SCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4626
+TRANS_FEAT(SCVTF_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4627
gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16)
4628
4620
-TRANS_FEAT(SCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4629
+TRANS_FEAT(SCVTF_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4630
gen_helper_sve_scvt_ss, a, 0, FPST_A64)
4622
-TRANS_FEAT(SCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4631
+TRANS_FEAT(SCVTF_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4632
gen_helper_sve_scvt_ds, a, 0, FPST_A64)
4633
4625
-TRANS_FEAT(SCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4634
+TRANS_FEAT(SCVTF_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4635
gen_helper_sve_scvt_sd, a, 0, FPST_A64)
4627
-TRANS_FEAT(SCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4636
+TRANS_FEAT(SCVTF_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4637
gen_helper_sve_scvt_dd, a, 0, FPST_A64)
4638
4630
-TRANS_FEAT(UCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4639
+TRANS_FEAT(UCVTF_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4640
gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16)
4632
-TRANS_FEAT(UCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4641
+TRANS_FEAT(UCVTF_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4642
gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16)
4634
-TRANS_FEAT(UCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4643
+TRANS_FEAT(UCVTF_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4644
gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16)
4645
4637
-TRANS_FEAT(UCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4646
+TRANS_FEAT(UCVTF_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4647
gen_helper_sve_ucvt_ss, a, 0, FPST_A64)
4639
-TRANS_FEAT(UCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4648
+TRANS_FEAT(UCVTF_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4649
gen_helper_sve_ucvt_ds, a, 0, FPST_A64)
4641
-TRANS_FEAT(UCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4650
+TRANS_FEAT(UCVTF_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4651
gen_helper_sve_ucvt_sd, a, 0, FPST_A64)
4652
4644
-TRANS_FEAT(UCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4653
+TRANS_FEAT(UCVTF_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz,
4654
gen_helper_sve_ucvt_dd, a, 0, FPST_A64)
4655
4656
/*
@@ -6691,23 +6700,23 @@ TRANS_FEAT(UADALP_zpzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzz,
6700
* SVE2 integer unary operations (predicated)
6701
*/
6702
6694
-TRANS_FEAT(URECPE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz,
6703
+TRANS_FEAT(URECPE_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz,
6704
a->esz == 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0)
6705
6697
-TRANS_FEAT(URSQRTE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz,
6706
+TRANS_FEAT(URSQRTE_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz,
6707
a->esz == 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0)
6708
6709
static gen_helper_gvec_3 * const sqabs_fns[4] = {
6710
gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
6711
gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
6712
};
6704
-TRANS_FEAT(SQABS, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0)
6713
+TRANS_FEAT(SQABS_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0)
6714
6715
static gen_helper_gvec_3 * const sqneg_fns[4] = {
6716
gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
6717
gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
6718
};
6710
-TRANS_FEAT(SQNEG, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
6719
+TRANS_FEAT(SQNEG_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
6720
6721
DO_ZPZZ(SQSHL, aa64_sme_or_sve2, sve2_sqshl)
6722
DO_ZPZZ(SQRSHL, aa64_sme_or_sve2, sve2_sqrshl)
@@ -7879,30 +7888,30 @@ static bool trans_RAX1(DisasContext *s, arg_RAX1 *a)
7888
return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a);
7889
}
7890
7882
-TRANS_FEAT(FCVTNT_sh, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7891
+TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7892
gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64)
7884
-TRANS_FEAT(FCVTNT_ds, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7893
+TRANS_FEAT(FCVTNT_ds_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7894
gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64)
7895
7887
-TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
7896
+TRANS_FEAT(BFCVTNT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
7897
gen_helper_sve_bfcvtnt, a, 0,
7898
s->fpcr_ah ? FPST_AH : FPST_A64)
7899
7891
-TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7900
+TRANS_FEAT(FCVTLT_hs_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7901
gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16)
7893
-TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7902
+TRANS_FEAT(FCVTLT_sd_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7903
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64)
7904
7896
-TRANS_FEAT(FCVTX_ds, aa64_sme_or_sve2, do_frint_mode, a,
7905
+TRANS_FEAT(FCVTX_ds_m, aa64_sme_or_sve2, do_frint_mode, a,
7906
FPROUNDING_ODD, gen_helper_sve_fcvt_ds)
7898
-TRANS_FEAT(FCVTXNT_ds, aa64_sme_or_sve2, do_frint_mode, a,
7907
+TRANS_FEAT(FCVTXNT_ds_m, aa64_sme_or_sve2, do_frint_mode, a,
7908
FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds)
7909
7910
static gen_helper_gvec_3_ptr * const flogb_fns[] = {
7911
NULL, gen_helper_flogb_h,
7912
gen_helper_flogb_s, gen_helper_flogb_d
7913
};
7905
-TRANS_FEAT(FLOGB, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
7914
+TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
7915
a, 0, a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
7916
7917
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)