include/tcg/tcg-op: extract memory operations to tcg-op-mem.h
This new header defines a new type for target virtual address, independent from TCGv and is parameterized by a new define TCG_ADDRESS_BITS (name was suggested by Paolo instead of TARGET_ADDRESS_BITS). By default, tcg-op.h include set this define to TARGET_LONG_BITS, but it's also possible to include only tcg-op-common.h and tcg-op-mem.h and set TCG_ADDRESS_BITS manually, which is what next commits will do. We preserve existing MIT license when extracting this new header. Implemented from: https://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/ Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Pierrick Bouvier committed
Apr 23, 2026 at 10:24 UTC
a8af0fb24dae7323284e39e2104f762ab47126ab
2 files changed
+129
-97
include/tcg/tcg-op-mem.h
new
+126
@@ -0,0 +1,126 @@
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+/* SPDX-License-Identifier: MIT */
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+/*
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+ * Target dependent memory related functions.
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+ *
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+ * Copyright (c) 2008 Fabrice Bellard
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+ */
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+
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+#ifndef TCG_TCG_OP_MEM_H
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+#define TCG_TCG_OP_MEM_H
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+
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+#ifndef TCG_ADDRESS_BITS
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+#error TCG_ADDRESS_BITS must be defined
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+#endif
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+
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+#if TCG_ADDRESS_BITS == 32
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+typedef TCGv_i32 TCGv_va;
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+#define TCG_TYPE_VA TCG_TYPE_I32
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+#define tcgv_va_temp tcgv_i32_temp
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+#define tcgv_va_temp_new tcg_temp_new_i32
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+#elif TCG_ADDRESS_BITS == 64
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+typedef TCGv_i64 TCGv_va;
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+#define TCG_TYPE_VA TCG_TYPE_I64
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+#define tcgv_va_temp tcgv_i64_temp
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+#define tcgv_va_temp_new tcg_temp_new_i64
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+#else
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+#error
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+#endif
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+
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+static inline void
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+tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m)
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+{
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+ tcg_gen_qemu_ld_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
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+}
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+
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+static inline void
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+tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m)
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+{
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+ tcg_gen_qemu_st_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
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+}
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+
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+static inline void
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+tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m)
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+{
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+ tcg_gen_qemu_ld_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
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+}
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+
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+static inline void
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+tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m)
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+{
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+ tcg_gen_qemu_st_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
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+}
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+
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+static inline void
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+tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m)
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+{
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+ tcg_gen_qemu_ld_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
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+}
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+
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+static inline void
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+tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m)
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+{
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+ tcg_gen_qemu_st_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
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+}
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+
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+#define DEF_ATOMIC2(N, S) \
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+ static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S v, \
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+ TCGArg i, MemOp m) \
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+ { N##_##S##_chk(r, tcgv_va_temp(a), v, i, m, TCG_TYPE_VA); }
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+
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+#define DEF_ATOMIC3(N, S) \
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+ static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S o, \
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+ TCGv_##S n, TCGArg i, MemOp m) \
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+ { N##_##S##_chk(r, tcgv_va_temp(a), o, n, i, m, TCG_TYPE_VA); }
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+
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+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32)
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+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64)
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+DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128)
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+
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+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32)
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+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64)
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+DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128)
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+
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+DEF_ATOMIC2(tcg_gen_atomic_xchg, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_xchg, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_xchg, i128)
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+
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64)
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+
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+DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64)
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+DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32)
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+DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
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+
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+#undef DEF_ATOMIC2
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+#undef DEF_ATOMIC3
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+
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+#endif /* TCG_TCG_OP_MEM_H */
include/tcg/tcg-op.h
+3
-97
@@ -16,6 +16,9 @@
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#error must include QEMU headers
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#endif
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+#define TCG_ADDRESS_BITS TARGET_LONG_BITS
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+#include "tcg/tcg-op-mem.h"
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+
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#if TARGET_LONG_BITS == 32
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# define TCG_TYPE_TL TCG_TYPE_I32
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#elif TARGET_LONG_BITS == 64
@@ -46,103 +49,6 @@ typedef TCGv_i64 TCGv;
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#error Unhandled TARGET_LONG_BITS value
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#endif
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-static inline void
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-tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m)
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-{
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- tcg_gen_qemu_ld_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
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-}
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-
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-static inline void
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-tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m)
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-{
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- tcg_gen_qemu_st_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
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-}
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-
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-static inline void
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-tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m)
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-{
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- tcg_gen_qemu_ld_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
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-}
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-
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-static inline void
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-tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m)
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-{
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- tcg_gen_qemu_st_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
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-}
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-
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-static inline void
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-tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m)
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-{
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- tcg_gen_qemu_ld_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
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-}
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-
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-static inline void
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-tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m)
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-{
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- tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL);
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-}
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-
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-#define DEF_ATOMIC2(N, S) \
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- static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \
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- TCGArg i, MemOp m) \
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- { N##_##S##_chk(r, tcgv_tl_temp(a), v, i, m, TCG_TYPE_TL); }
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-
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-#define DEF_ATOMIC3(N, S) \
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- static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S o, \
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- TCGv_##S n, TCGArg i, MemOp m) \
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- { N##_##S##_chk(r, tcgv_tl_temp(a), o, n, i, m, TCG_TYPE_TL); }
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-
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-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32)
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-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64)
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-DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128)
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-
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-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32)
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-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64)
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-DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128)
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-
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-DEF_ATOMIC2(tcg_gen_atomic_xchg, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_xchg, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_xchg, i128)
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-
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64)
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-
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-DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64)
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-DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32)
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-DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
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-
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-#undef DEF_ATOMIC2
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-#undef DEF_ATOMIC3
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-
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#if TARGET_LONG_BITS == 64
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#define tcg_gen_movi_tl tcg_gen_movi_i64
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#define tcg_gen_mov_tl tcg_gen_mov_i64