@samitouri / QOSamiQemu / commits / a8dc227c83

target/riscv: Expose and document the CPU 'big-endian' property

Now that the full big-endian data path is in place (runtime MSTATUS bits, boot code, and page-table walks), expose the "big-endian" property to users via DEFINE_PROP_BOOL and document it in docs/system/target-riscv.rst. Document that the property models fixed-endian hardware: it selects harts whose MBE/SBE/UBE fields are fixed to 1, and it does not model a mixed-endian implementation where software can toggle those bits at runtime. The property can be enabled from the command line, e.g.: -cpu <cpu>,big-endian=on Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-ID: <20260527201348.29511-12-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Djordje Todorovic committed May 27, 2026 at 22:13 UTC a8dc227c836436b9429de4330ad6bf5e8481e940
2 files changed +30
docs/system/target-riscv.rst
+29
@@ -95,3 +95,32 @@ the images they need.
95 * ``-bios <file>``
96
97 Tells QEMU to load the specified file as the firmware.
98 +
99 +RISC-V CPU endianness
100 +---------------------
101 +
102 +The RISC-V ISA specifies that instruction fetches are always little-endian,
103 +while data accesses can be either little-endian or big-endian under control
104 +of the MSTATUS ``MBE``/``SBE``/``UBE`` bits (see section 3.1.6.5, "Memory
105 +Endianness", in the RISC-V Privileged Specification).
106 +
107 +QEMU implements the full data-endianness behaviour described by those bits.
108 +In addition, the RISC-V CPU object exposes a ``big-endian`` boolean property
109 +which models a big-endian-only hardware implementation, where the
110 +``MBE``/``SBE``/``UBE`` bits are hardwired to 1. When the property is set,
111 +the CPU is reset with all three bits initialised to 1, so the guest starts
112 +executing in big-endian data mode from the reset vector. The property is a
113 +static, per-CPU hardware configuration option and is not meant to be toggled
114 +at runtime.
115 +
116 +The property does not model a mixed-endian implementation where software can
117 +toggle ``MBE``/``SBE``/``UBE`` at runtime. QEMU's RISC-V CPUs treat these
118 +fields as fixed by the CPU configuration: they are reset to 0 by default and
119 +to 1 when ``big-endian`` is enabled.
120 +
121 +The property can be enabled from the command line, for example::
122 +
123 + -cpu <cpu>,big-endian=on
124 +
125 +No upstream CPU model currently defaults to big-endian; the property is
126 +provided so that big-endian-only RISC-V CPU variants can be modelled.
target/riscv/cpu.c
+1
@@ -2525,6 +2525,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
2525
2526 static const Property riscv_cpu_properties[] = {
2527 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
2528 + DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false),
2529
2530 {.name = "pmu-mask", .info = &prop_pmu_mask},
2531 {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */