target/arm: Enable FEAT_FP8 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
a918a18f0ef682d57e9f34bbdcf2468580131137
3 files changed
+10
docs/system/arm/emulation.rst
+1
@@ -75,6 +75,7 @@ the following architecture extensions:
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- FEAT_FHM (Floating-point half-precision multiplication instructions)
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- FEAT_FP (Floating Point extensions)
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- FEAT_FP16 (Half-precision floating-point data processing)
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+- FEAT_FP8 (FP8 convert instructions)
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- FEAT_FPAC (Faulting on AUT* instructions)
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- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
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- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
linux-user/aarch64/elfload.c
+3
@@ -222,6 +222,9 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
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GET_FEATURE_ID(aa64_faminmax, ARM_HWCAP2_A64_FAMINMAX);
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GET_FEATURE_ID(aa64_fpmr, ARM_HWCAP2_A64_FPMR);
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GET_FEATURE_ID(aa64_lut, ARM_HWCAP2_A64_LUT);
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+ GET_FEATURE_ID(aa64_f8cvt, ARM_HWCAP2_A64_F8CVT |
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+ ARM_HWCAP2_A64_F8E4M3 |
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+ ARM_HWCAP2_A64_F8E5M2);
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return hwcaps;
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}
target/arm/tcg/cpu64.c
+6
@@ -1397,6 +1397,12 @@ void aarch64_max_tcg_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
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SET_IDREG(isar, ID_AA64SMFR0, t);
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+ t = GET_IDREG(isar, ID_AA64FPFR0);
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+ t = FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* FEAT_FP8 */
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+ t = FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* FEAT_FP8 */
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+ t = FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* FEAT_FP8 */
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+ SET_IDREG(isar, ID_AA64FPFR0, t);
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+
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/* Replicate the same data to the 32-bit id registers. */
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aa32_max_features(cpu);
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