target/riscv: Allow UXL to be 3 in mstatus on rv128
Valid UXL field values for mstatus were restricted to fix a reported issue, but this inadvertently broke the experimental rv128 support where a value of 3 validly represents 128-bit execution. Update the mstatus write logic to permit UXL=3 when running on an rv128 CPU. Fixes: dcd028517749 ("target/riscv: Apply UXL WARL handling to vsstatus") Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu@processmission.com> Message-ID: <20260819105655.33391-3-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot committed
Aug 19, 2026 at 12:56 UTC
a9779d24be31338d90aa19a560e69cc4c9660627
1 file changed
+2
-2
target/riscv/tcg/csr.c
+2
-2
@@ -2014,8 +2014,8 @@ static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
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RISCVMXL xl = riscv_cpu_mxl(env);
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uint64_t uxl = get_field(val, field);
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- if (uxl == MXL_RV128) {
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- uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
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+ if (xl != MXL_RV128 && uxl == MXL_RV128) {
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+ uxl = xl;
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val = set_field(val, field, uxl);
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}
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