target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:20 UTC
aa0d730495b360cf9a1b0a5724fd9ca6768891a2
4 files changed
+73
target/arm/tcg/fp8_helper.c
+47
@@ -138,3 +138,50 @@ void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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fp8_cvt_finish(env, &ctx);
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}
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+
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+void HELPER(sme2_bfcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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+{
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+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);
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+ fp8_input_fn *input_fmt = fp8_input_fmt[ctx.f8fmt];
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+ uint8_t *n = vn;
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+ uint16_t *d0 = vd;
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+ uint16_t *d1 = vd + sizeof(ARMVectorReg);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 2;
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+ ARMVectorReg scratch;
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+
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+ if (vectors_overlap(vd, 2, vn, 1)) {
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+ n = memcpy(&scratch, vn, oprsz);
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+ }
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+
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+ for (size_t i = 0; i < nelem; ++i) {
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+ d0[H2(i)] = fcvt_fp8_to_b16(n[H1(i)], input_fmt,
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+ ctx.scale, &ctx.stat);
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+ }
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+ for (size_t i = 0; i < nelem; ++i) {
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+ d1[H2(i)] = fcvt_fp8_to_b16(n[H1(i + nelem)], input_fmt,
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+ ctx.scale, &ctx.stat);
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+ }
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+
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+ fp8_cvt_finish(env, &ctx);
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+}
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+
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+void HELPER(sme2_bfcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
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+{
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+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);
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+ fp8_input_fn *input_fmt = fp8_input_fmt[ctx.f8fmt];
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+ uint8_t *n = vn;
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+ uint16_t *d0 = vd;
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+ uint16_t *d1 = vd + sizeof(ARMVectorReg);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nelem = oprsz / 2;
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+
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+ for (size_t i = 0; i < nelem; ++i) {
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+ uint8_t e0 = n[H1(2 * i + 0)];
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+ uint8_t e1 = n[H1(2 * i + 1)];
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+ d0[H2(i)] = fcvt_fp8_to_b16(e0, input_fmt, ctx.scale, &ctx.stat);
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+ d1[H2(i)] = fcvt_fp8_to_b16(e1, input_fmt, ctx.scale, &ctx.stat);
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+ }
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+
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+ fp8_cvt_finish(env, &ctx);
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+}
target/arm/tcg/helper-fp8-defs.h
+2
@@ -5,3 +5,5 @@
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DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
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+DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
target/arm/tcg/sme.decode
+5
@@ -853,6 +853,11 @@ UUNPK_4bh 11000001 011 10101 111000 ....0 ...01 @zz_4x2_n1
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UUNPK_4hs 11000001 101 10101 111000 ....0 ...01 @zz_4x2_n1
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UUNPK_4sd 11000001 111 10101 111000 ....0 ...01 @zz_4x2_n1
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+BF1CVT 11000001 011 00110 111000 ..... ....0 @zz_2x1
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+BF2CVT 11000001 111 00110 111000 ..... ....0 @zz_2x1
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+BF1CVTL 11000001 011 00110 111000 ..... ....1 @zz_2x1
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+BF2CVTL 11000001 111 00110 111000 ..... ....1 @zz_2x1
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+
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ZIP_4 11000001 esz:2 1 10110 111000 ...00 ... 00 \
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&zz_e zd=%zd_ax4 zn=%zn_ax4
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ZIP_4 11000001 001 10111 111000 ...00 ... 00 \
target/arm/tcg/translate-sme.c
+19
@@ -22,6 +22,7 @@
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#include "helper-a64.h"
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#include "helper-sme.h"
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#include "helper-sve.h"
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+#include "helper-fp8.h"
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#include "translate.h"
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#include "translate-a64.h"
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#include "tcg/tcg-op.h"
@@ -1532,6 +1533,24 @@ TRANS_FEAT(UUNPK_4bh, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_bh)
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TRANS_FEAT(UUNPK_4hs, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_hs)
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TRANS_FEAT(UUNPK_4sd, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_sd)
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+static bool do_f8cvt(DisasContext *s, arg_zz_n *a,
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+ gen_helper_gvec_2_ptr *fn, bool issrc2)
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+{
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+ if (fpmr_access_check(s) && sme_sm_enabled_check(s)) {
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+ int svl = streaming_vec_reg_size(s);
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+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->zd),
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+ vec_full_reg_offset(s, a->zn),
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+ tcg_env, svl, svl,
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+ issrc2 | (FPST_ZA << 2), fn);
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+ }
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+ return true;
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+}
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+
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+TRANS_FEAT(BF1CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 0)
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+TRANS_FEAT(BF2CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 1)
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+TRANS_FEAT(BF1CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 0)
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+TRANS_FEAT(BF2CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 1)
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+
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static bool do_zipuzp_4(DisasContext *s, arg_zz_e *a,
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gen_helper_gvec_2 * const fn[5])
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{