@samitouri / QOSamiQemu / commits / aa42300f86

target/arm: Use FPST_A64_F16 for SVE FCVTLT_hs

We should be using the F16-specific float_status for conversions from half-precision, because halfprec inputs never set Input Denormal. If we use the FPST_A64 fpstatus then we will incorrectly set FPCR.IDC for input-denormals when FPCR.AH=1. In commit e07b48995aaa we updated most of the halfprec-to-other conversion insns to use FPST_A64_F16 as part of implementing FEAT_AHP. However we missed the SVE FCVTLT instruction, which has a halfprec-to-single encoding. Correct the FPST we use for the hs variant of FCVTLT. Cc: qemu-stable@nongnu.org Fixes: e07b48995aaa ("target/arm: Use FPST_A64_F16 for halfprec-to-other conversions")a Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260521122913.1565011-3-peter.maydell@linaro.org

Peter Maydell committed May 21, 2026 at 13:29 UTC aa42300f86d172d7252f0cb95c2efd7570ad6b8f
1 file changed +1 -1
target/arm/tcg/translate-sve.c
+1 -1
@@ -7827,7 +7827,7 @@ TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
7827 s->fpcr_ah ? FPST_AH : FPST_A64)
7828
7829 TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7830 - gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64)
7830 + gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16)
7831 TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
7832 gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64)
7833