target/arm: Introduce FPMR
Introduce the special register FPMR and its fields. Migrate it when present. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260522220306.235200-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
May 22, 2026 at 15:02 UTC
aa4d11f0f2f32b3b6495eba9943891cc56923bf5
6 files changed
+52
-1
target/arm/cpregs.h
+5
@@ -149,6 +149,11 @@ enum {
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* should not trap to EL2 when HCR_EL2.NV is set.
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*/
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ARM_CP_NV_NO_TRAP = 1 << 22,
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+ /*
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+ * Flag: Access check for this sysreg is constrained by the
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+ * ARM pseudocode function CheckFPMREnabled().
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+ */
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+ ARM_CP_FPMR = 1 << 23,
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};
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/*
target/arm/cpu-features.h
+5
@@ -1192,6 +1192,11 @@ static inline bool isar_feature_aa64_gcie(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64PFR2, GCIE) != 0;
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}
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+static inline bool isar_feature_aa64_fpmr(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, FPMR) != 0;
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+}
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+
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static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
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{
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return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;
target/arm/cpu.h
+1
@@ -713,6 +713,7 @@ typedef struct CPUArchState {
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*/
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uint64_t fpsr;
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uint64_t fpcr;
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+ uint64_t fpmr;
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uint32_t xregs[16];
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target/arm/helper.c
+11
-1
@@ -6229,6 +6229,14 @@ static const ARMCPRegInfo aie_reginfo[] = {
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.type = ARM_CP_CONST, .resetvalue = 0 },
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};
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+static const ARMCPRegInfo fpmr_reginfo[] = {
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+ { .name = "FPMR", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 4, .opc2 = 2,
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+ .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_FPMR,
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+ .fieldoffset = offsetof(CPUARMState, vfp.fpmr),
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+ }
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+};
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+
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void register_cp_regs_for_features(ARMCPU *cpu)
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{
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/* Register all the coprocessor registers based on feature bits */
@@ -7502,10 +7510,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, mec_mte_reginfo);
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}
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}
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-
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if (cpu_isar_feature(aa64_aie, cpu)) {
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define_arm_cp_regs(cpu, aie_reginfo);
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}
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+ if (cpu_isar_feature(aa64_fpmr, cpu)) {
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+ define_arm_cp_regs(cpu, fpmr_reginfo);
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+ }
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if (cpu_isar_feature(any_predinv, cpu)) {
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define_arm_cp_regs(cpu, predinv_reginfo);
target/arm/internals.h
+10
@@ -293,6 +293,16 @@ FIELD(CNTHCTL, EVNTIS, 17, 1)
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FIELD(CNTHCTL, CNTVMASK, 18, 1)
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FIELD(CNTHCTL, CNTPMASK, 19, 1)
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+FIELD(FPMR, F8S1, 0, 3)
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+FIELD(FPMR, F8S2, 3, 3)
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+FIELD(FPMR, F8D, 6, 3)
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+FIELD(FPMR, OSM, 14, 1)
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+FIELD(FPMR, OSC, 15, 1)
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+FIELD(FPMR, LSCALE, 16, 7)
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+FIELD(FPMR, NSCALE, 24, 8)
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+FIELD(FPMR, NSCALE_F16, 24, 5)
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+FIELD(FPMR, LSCALE2, 32, 6)
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+
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/* We use a few fake FSR values for internal purposes in M profile.
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* M profile cores don't have A/R format FSRs, but currently our
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* get_phys_addr() code assumes A/R profile and reports failures via
target/arm/machine.c
+20
@@ -960,6 +960,25 @@ static const VMStateDescription vmstate_syndrome64 = {
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},
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};
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+static bool fpmr_needed(void *opaque)
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+{
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+ ARMCPU *cpu = opaque;
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+
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+ return arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
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+ && cpu_isar_feature(aa64_fpmr, cpu);
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+}
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+
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+static const VMStateDescription vmstate_fpmr = {
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+ .name = "cpu/fpmr",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .needed = fpmr_needed,
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+ .fields = (const VMStateField[]) {
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+ VMSTATE_UINT64(env.vfp.fpmr, ARMCPU),
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+ VMSTATE_END_OF_LIST()
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+ },
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+};
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+
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static int cpu_pre_save(void *opaque)
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{
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ARMCPU *cpu = opaque;
@@ -1323,6 +1342,7 @@ const VMStateDescription vmstate_arm_cpu = {
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&vmstate_syndrome64,
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&vmstate_pstate64,
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&vmstate_event,
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+ &vmstate_fpmr,
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NULL
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}
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};