target/arm: Implement BFTMOPA (non-widening)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260713230244.70174-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Aug 11, 2026 at 20:14 UTC
aa8965de49e66cc4c04dbd99274d108418687a8e
5 files changed
+15
target/arm/cpu-features.h
+5
@@ -1842,6 +1842,11 @@ static inline bool isar_feature_aa64_sme_mop4_i16i64(const ARMISARegisters *id)
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return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_i16i64(id);
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}
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+static inline bool isar_feature_aa64_sme_tmop_b16b16(const ARMISARegisters *id)
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+{
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+ return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_b16b16(id);
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+}
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+
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static inline bool isar_feature_aa64_sme_tmop_f16f16(const ARMISARegisters *id)
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{
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return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f16f16(id);
target/arm/tcg/helper-sme-defs.h
+1
@@ -405,5 +405,6 @@ DEF_HELPER_FLAGS_4(sme_usmop4s_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sme_usmop4a_dh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sme_usmop4s_dh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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+DEF_HELPER_FLAGS_6(sme_bftmopa_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_6(sme_ftmopa_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
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DEF_HELPER_FLAGS_6(sme_ftmopa_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
target/arm/tcg/sme.decode
+1
@@ -1142,5 +1142,6 @@ USMOP4_dh 1010 0001 110. ...0 0000 00.. ..0. 1... @mop4_o3
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@tmop_o2 .... .... ... zm:5 ... ... .... idx:2 .. zad:2 \
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&tmop zn=%zn_ax2 zk=%tmop_zk
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+BFTMOPA_hh 1000 0001 011 ..... 000 ... .... .. 100 . @tmop_o1
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FTMOPA_hh 1000 0001 010 ..... 000 ... .... .. 100 . @tmop_o1
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FTMOPA_ss 1000 0000 010 ..... 000 ... .... .. 00 .. @tmop_o2
target/arm/tcg/sme_helper.c
+6
@@ -2831,6 +2831,12 @@ void HELPER(sme_bfmop4a_hh)(void *vza, void *vzn, void *vzm,
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sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(bfloat16), inner_bfmop4a_hh);
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}
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+void HELPER(sme_bftmopa_hh)(void *vza, void *vzn, void *vzm, void *vzk,
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+ float_status *fpst, uint32_t desc)
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+{
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+ sme_tmop(vza, vzn, vzm, vzk, fpst, desc, MO_16, inner_bfmop4a_hh);
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+}
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+
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static void inner_bfmop4s_hh(void *vd, void *vn, void *vm, void *vinfo)
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{
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bfloat16 *d = vd, *n = vn, *m = vm;
target/arm/tcg/translate-sme.c
+2
@@ -2156,6 +2156,8 @@ static bool do_tmop_fp(DisasContext *s, arg_tmop *a, MemOp esz,
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return true;
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}
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+TRANS_FEAT(BFTMOPA_hh, aa64_sme_tmop_b16b16, do_tmop_fp,
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+ a, MO_16, FPST_ZA, gen_helper_sme_bftmopa_hh)
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TRANS_FEAT(FTMOPA_hh, aa64_sme_tmop_f16f16, do_tmop_fp,
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a, MO_16, FPST_ZA_F16, gen_helper_sme_ftmopa_hh)
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TRANS_FEAT(FTMOPA_ss, aa64_sme_tmop, do_tmop_fp,