target/arm/machine: Use VMSTATE_VARRAY_INT32_ALLOC for cpreg arrays
This removes the need for explicitly allocating cpreg_vmstate arrays. On post save we simply point to cpreg arrays and set the length accordingly. Remove VMSTATE_VARRAY_INT32 for cpreg_vmstate_array_len as now the array is dynamically allocated. Also add a trace point on post_load to trace potential mismatch between the number of incoming cpregs versus current ones. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260304101625.1962633-3-eric.auger@redhat.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger committed
Mar 6, 2026 at 09:01 UTC
ab2ddc7b662d34c242ddfcfbe35996417b047ce2
5 files changed
+35
-30
target/arm/helper.c
-5
@@ -265,15 +265,10 @@ void arm_init_cpreg_list(ARMCPU *cpu)
265
if (arraylen) {
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cpu->cpreg_indexes = g_new(uint64_t, arraylen);
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cpu->cpreg_values = g_new(uint64_t, arraylen);
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- cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
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- cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
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} else {
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cpu->cpreg_indexes = NULL;
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cpu->cpreg_values = NULL;
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- cpu->cpreg_vmstate_indexes = NULL;
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- cpu->cpreg_vmstate_values = NULL;
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}
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- cpu->cpreg_vmstate_array_len = arraylen;
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cpu->cpreg_array_len = 0;
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g_hash_table_foreach(cpu->cp_regs, add_cpreg_to_list, cpu);
target/arm/kvm.c
-5
@@ -864,12 +864,7 @@ static int kvm_arm_init_cpreg_list(ARMCPU *cpu)
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cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
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cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
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- cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
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- arraylen);
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- cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
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- arraylen);
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cpu->cpreg_array_len = arraylen;
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- cpu->cpreg_vmstate_array_len = arraylen;
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for (i = 0, arraylen = 0; i < rlp->n; i++) {
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uint64_t regidx = rlp->reg[i];
target/arm/machine.c
+32
-13
@@ -1,5 +1,6 @@
1
#include "qemu/osdep.h"
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#include "cpu.h"
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+#include "trace.h"
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#include "qemu/error-report.h"
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#include "system/kvm.h"
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#include "system/tcg.h"
@@ -984,11 +985,14 @@ static int cpu_pre_save(void *opaque)
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}
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}
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+ /*
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+ * On outbound migration, send the data in our cpreg_{values,indexes}
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+ * arrays. The migration code will not allocate anything, but just
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+ * reads the data pointed to by the VMSTATE_VARRAY_INT32_ALLOC() fields.
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+ */
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+ cpu->cpreg_vmstate_indexes = cpu->cpreg_indexes;
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+ cpu->cpreg_vmstate_values = cpu->cpreg_values;
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cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
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- memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
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- cpu->cpreg_array_len * sizeof(uint64_t));
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- memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
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- cpu->cpreg_array_len * sizeof(uint64_t));
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return 0;
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}
@@ -1001,6 +1005,9 @@ static int cpu_post_save(void *opaque)
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pmu_op_finish(&cpu->env);
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}
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+ cpu->cpreg_vmstate_indexes = NULL;
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+ cpu->cpreg_vmstate_values = NULL;
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+
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return 0;
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}
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@@ -1034,6 +1041,9 @@ static int cpu_pre_load(void *opaque)
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pmu_op_start(env);
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}
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+ g_assert(!cpu->cpreg_vmstate_indexes);
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+ g_assert(!cpu->cpreg_vmstate_values);
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+
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return 0;
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}
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@@ -1043,6 +1053,9 @@ static int cpu_post_load(void *opaque, int version_id)
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CPUARMState *env = &cpu->env;
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int i, v;
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+ trace_cpu_post_load(cpu->cpreg_vmstate_array_len,
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+ cpu->cpreg_array_len);
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+
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/*
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* Handle migration compatibility from old QEMU which didn't
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* send the irq-line-state subsection. A QEMU without it did not
@@ -1094,6 +1107,11 @@ static int cpu_post_load(void *opaque, int version_id)
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}
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}
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+ g_free(cpu->cpreg_vmstate_indexes);
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+ g_free(cpu->cpreg_vmstate_values);
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+ cpu->cpreg_vmstate_indexes = NULL;
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+ cpu->cpreg_vmstate_values = NULL;
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+
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/*
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* Misaligned thumb pc is architecturally impossible. Fail the
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* incoming migration. For TCG it would trigger the assert in
@@ -1167,16 +1185,17 @@ const VMStateDescription vmstate_arm_cpu = {
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VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
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VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
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VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
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- /* The length-check must come before the arrays to avoid
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- * incoming data possibly overflowing the array.
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+ /*
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+ * The length must come before the arrays so we can
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+ * allocate the arrays before their data arrives
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*/
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- VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
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- VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
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- cpreg_vmstate_array_len,
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- 0, vmstate_info_uint64, uint64_t),
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- VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
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- cpreg_vmstate_array_len,
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- 0, vmstate_info_uint64, uint64_t),
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+ VMSTATE_INT32(cpreg_vmstate_array_len, ARMCPU),
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+ VMSTATE_VARRAY_INT32_ALLOC(cpreg_vmstate_indexes, ARMCPU,
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+ cpreg_vmstate_array_len,
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+ 0, vmstate_info_uint64, uint64_t),
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+ VMSTATE_VARRAY_INT32_ALLOC(cpreg_vmstate_values, ARMCPU,
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+ cpreg_vmstate_array_len,
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+ 0, vmstate_info_uint64, uint64_t),
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VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
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VMSTATE_UINT64(env.exclusive_val, ARMCPU),
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VMSTATE_UINT64(env.exclusive_high, ARMCPU),
target/arm/trace-events
+3
@@ -26,3 +26,6 @@ arm_powerctl_reset_cpu(uint64_t mp_aff) "cpu %" PRIu64
26
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# tcg/psci.c and hvf/hvf.c
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arm_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpuid=0x%x"
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+
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+# machine.c
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+cpu_post_load(uint32_t cpreg_vmstate_array_len, uint32_t cpreg_array_len) "cpreg_vmstate_array_len=%d cpreg_array_len=%d"
target/arm/whpx/whpx-all.c
-7
@@ -783,12 +783,6 @@ int whpx_init_vcpu(CPUState *cpu)
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sregs_match_len);
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arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
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sregs_match_len);
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- arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
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- arm_cpu->cpreg_vmstate_indexes,
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- sregs_match_len);
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- arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
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- arm_cpu->cpreg_vmstate_values,
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- sregs_match_len);
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memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
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@@ -807,7 +801,6 @@ int whpx_init_vcpu(CPUState *cpu)
801
}
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}
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arm_cpu->cpreg_array_len = sregs_cnt;
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- arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
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assert(write_cpustate_to_list(arm_cpu, false));
806