target/arm: Use generic tcg_gen_revbit*
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson committed
Jul 30, 2026 at 11:09 UTC
ab86f82ba9f190d3e9a46f6f354333f0b29ee905
6 files changed
+3
-15
target/arm/tcg/helper-a64-defs.h
-1
@@ -18,7 +18,6 @@
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*/
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DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
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-DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
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DEF_HELPER_2(msr_i_spsel, void, env, i32)
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DEF_HELPER_2(msr_i_daifset, void, env, i32)
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DEF_HELPER_2(msr_i_daifclear, void, env, i32)
target/arm/tcg/helper-a64.c
-5
@@ -69,11 +69,6 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den)
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return num / den;
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}
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-uint64_t HELPER(rbit64)(uint64_t x)
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-{
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- return revbit64(x);
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-}
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-
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void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)
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{
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update_spsel(env, imm);
target/arm/tcg/helper-defs.h
-1
@@ -10,7 +10,6 @@ DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
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DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32)
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DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32)
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-DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32)
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#define PAS_OP(pfx) \
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DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \
target/arm/tcg/op_helper.c
-5
@@ -172,11 +172,6 @@ uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den)
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return num / den;
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}
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-uint32_t HELPER(rbit)(uint32_t x)
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-{
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- return revbit32(x);
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-}
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-
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uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
target/arm/tcg/translate-a64.c
+2
-2
@@ -8963,7 +8963,7 @@ static void gen_wrap2_i32(TCGv_i64 d, TCGv_i64 n, NeonGenOneOpFn fn)
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static void gen_rbit32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
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{
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- gen_wrap2_i32(tcg_rd, tcg_rn, gen_helper_rbit);
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+ tcg_gen_revbit32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ);
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}
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static void gen_rev16_xx(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 mask)
@@ -8998,7 +8998,7 @@ static void gen_rev32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
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tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32);
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}
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-TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? gen_helper_rbit64 : gen_rbit32)
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+TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? tcg_gen_revbit64_i64 : gen_rbit32)
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TRANS(REV16, gen_rr, a->rd, a->rn, a->sf ? gen_rev16_64 : gen_rev16_32)
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TRANS(REV32, gen_rr, a->rd, a->rn, a->sf ? gen_rev32 : gen_rev_32)
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TRANS(REV64, gen_rr, a->rd, a->rn, tcg_gen_bswap64_i64)
target/arm/tcg/translate.c
+1
-1
@@ -4835,7 +4835,7 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a)
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if (!ENABLE_ARCH_6T2) {
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return false;
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}
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- return op_rr(s, a, gen_helper_rbit);
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+ return op_rr(s, a, tcg_gen_revbit32_i32);
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}
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/*