target/mips: decode Octeon HSH and SHA3 COP2 selectors
Add explicit decodetree entries and translator bindings for the Octeon HSH shared-window selectors and SHA3 operation selectors. Simple SHA3 DAT register moves and XORDAT selectors use direct TCG transfers, while HSH operation selectors and SHA3 STARTOP remain helper-backed for their visible side effects. Keep HSH/SHA3 decode separate from direct register transfers because the shared hash-window aliases and side-effecting operations need their own selector coverage. Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-16-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
James Hilliard committed
Jun 8, 2026 at 12:59 UTC
ac28df97e51dd6c7cd80d7003ef189c1df1db17b
2 files changed
+179
target/mips/tcg/octeon.decode
+77
@@ -113,6 +113,7 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx
113
CVM_MF_HSH_DAT4 010010 00001 rt:5 0000 0000 0100 0100 &cp2
114
CVM_MF_HSH_DAT5 010010 00001 rt:5 0000 0000 0100 0101 &cp2
115
CVM_MF_HSH_DAT6 010010 00001 rt:5 0000 0000 0100 0110 &cp2
116
+ CVM_MF_SHA3_DAT24 010010 00001 rt:5 0000 0000 0101 0000 &cp2
117
CVM_MF_3DES_KEY0 010010 00001 rt:5 0000 0000 1000 0000 &cp2
118
CVM_MF_3DES_KEY1 010010 00001 rt:5 0000 0000 1000 0001 &cp2
119
CVM_MF_3DES_KEY2 010010 00001 rt:5 0000 0000 1000 0010 &cp2
@@ -137,6 +138,30 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx
138
CVM_MF_GFM_MUL_REFLECT1 010010 00001 rt:5 0000 0000 0101 1001 &cp2
139
CVM_MF_GFM_RESINP_REFLECT0 010010 00001 rt:5 0000 0000 0101 1010 &cp2
140
CVM_MF_GFM_RESINP_REFLECT1 010010 00001 rt:5 0000 0000 0101 1011 &cp2
141
+ CVM_MF_HSH_DATW0 010010 00001 rt:5 0000 0010 0100 0000 &cp2
142
+ CVM_MF_HSH_DATW1 010010 00001 rt:5 0000 0010 0100 0001 &cp2
143
+ CVM_MF_HSH_DATW2 010010 00001 rt:5 0000 0010 0100 0010 &cp2
144
+ CVM_MF_HSH_DATW3 010010 00001 rt:5 0000 0010 0100 0011 &cp2
145
+ CVM_MF_HSH_DATW4 010010 00001 rt:5 0000 0010 0100 0100 &cp2
146
+ CVM_MF_HSH_DATW5 010010 00001 rt:5 0000 0010 0100 0101 &cp2
147
+ CVM_MF_HSH_DATW6 010010 00001 rt:5 0000 0010 0100 0110 &cp2
148
+ CVM_MF_HSH_DATW7 010010 00001 rt:5 0000 0010 0100 0111 &cp2
149
+ CVM_MF_HSH_DATW8 010010 00001 rt:5 0000 0010 0100 1000 &cp2
150
+ CVM_MF_HSH_DATW9 010010 00001 rt:5 0000 0010 0100 1001 &cp2
151
+ CVM_MF_HSH_DATW10 010010 00001 rt:5 0000 0010 0100 1010 &cp2
152
+ CVM_MF_HSH_DATW11 010010 00001 rt:5 0000 0010 0100 1011 &cp2
153
+ CVM_MF_HSH_DATW12 010010 00001 rt:5 0000 0010 0100 1100 &cp2
154
+ CVM_MF_HSH_DATW13 010010 00001 rt:5 0000 0010 0100 1101 &cp2
155
+ CVM_MF_HSH_DATW14 010010 00001 rt:5 0000 0010 0100 1110 &cp2
156
+ CVM_MF_HSH_DATW15 010010 00001 rt:5 0000 0010 0100 1111 &cp2
157
+ CVM_MF_HSH_IVW0 010010 00001 rt:5 0000 0010 0101 0000 &cp2
158
+ CVM_MF_HSH_IVW1 010010 00001 rt:5 0000 0010 0101 0001 &cp2
159
+ CVM_MF_HSH_IVW2 010010 00001 rt:5 0000 0010 0101 0010 &cp2
160
+ CVM_MF_HSH_IVW3 010010 00001 rt:5 0000 0010 0101 0011 &cp2
161
+ CVM_MF_HSH_IVW4 010010 00001 rt:5 0000 0010 0101 0100 &cp2
162
+ CVM_MF_HSH_IVW5 010010 00001 rt:5 0000 0010 0101 0101 &cp2
163
+ CVM_MF_HSH_IVW6 010010 00001 rt:5 0000 0010 0101 0110 &cp2
164
+ CVM_MF_HSH_IVW7 010010 00001 rt:5 0000 0010 0101 0111 &cp2
165
CVM_MF_GFM_MUL0 010010 00001 rt:5 0000 0010 0101 1000 &cp2
166
CVM_MF_GFM_MUL1 010010 00001 rt:5 0000 0010 0101 1001 &cp2
167
CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 1010 &cp2
@@ -153,6 +178,10 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx
178
CVM_MT_HSH_IV1 010010 00101 rt:5 0000 0000 0100 1001 &cp2
179
CVM_MT_HSH_IV2 010010 00101 rt:5 0000 0000 0100 1010 &cp2
180
CVM_MT_HSH_IV3 010010 00101 rt:5 0000 0000 0100 1011 &cp2
181
+ CVM_MT_SHA3_DAT24 010010 00101 rt:5 0000 0000 0101 0000 &cp2
182
+ CVM_MT_SHA3_DAT15 010010 00101 rt:5 0000 0000 0101 0001 &cp2
183
+ # Cavium SDK code uses 0x0057 as a STARTSHA1 compatibility alias.
184
+ CVM_MT_HSH_STARTSHA1_COMPAT 010010 00101 rt:5 0000 0000 0101 0111 &cp2
185
CVM_MT_GFM_MUL_REFLECT0 010010 00101 rt:5 0000 0000 0101 1000 &cp2
186
CVM_MT_GFM_MUL_REFLECT1 010010 00101 rt:5 0000 0000 0101 1001 &cp2
187
CVM_MT_GFM_XOR0_REFLECT 010010 00101 rt:5 0000 0000 0101 1100 &cp2
@@ -182,19 +211,67 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx
211
CVM_MT_CRC_BYTE_REFLECT 010010 00101 rt:5 0000 0010 0001 0100 &cp2
212
CVM_MT_CRC_HALF_REFLECT 010010 00101 rt:5 0000 0010 0001 0101 &cp2
213
CVM_MT_CRC_WORD_REFLECT 010010 00101 rt:5 0000 0010 0001 0110 &cp2
214
+ CVM_MT_HSH_DATW0 010010 00101 rt:5 0000 0010 0100 0000 &cp2
215
+ CVM_MT_HSH_DATW1 010010 00101 rt:5 0000 0010 0100 0001 &cp2
216
+ CVM_MT_HSH_DATW2 010010 00101 rt:5 0000 0010 0100 0010 &cp2
217
+ CVM_MT_HSH_DATW3 010010 00101 rt:5 0000 0010 0100 0011 &cp2
218
+ CVM_MT_HSH_DATW4 010010 00101 rt:5 0000 0010 0100 0100 &cp2
219
+ CVM_MT_HSH_DATW5 010010 00101 rt:5 0000 0010 0100 0101 &cp2
220
+ CVM_MT_HSH_DATW6 010010 00101 rt:5 0000 0010 0100 0110 &cp2
221
+ CVM_MT_HSH_DATW7 010010 00101 rt:5 0000 0010 0100 0111 &cp2
222
+ CVM_MT_HSH_DATW8 010010 00101 rt:5 0000 0010 0100 1000 &cp2
223
+ CVM_MT_HSH_DATW9 010010 00101 rt:5 0000 0010 0100 1001 &cp2
224
+ CVM_MT_HSH_DATW10 010010 00101 rt:5 0000 0010 0100 1010 &cp2
225
+ CVM_MT_HSH_DATW11 010010 00101 rt:5 0000 0010 0100 1011 &cp2
226
+ CVM_MT_HSH_DATW12 010010 00101 rt:5 0000 0010 0100 1100 &cp2
227
+ CVM_MT_HSH_DATW13 010010 00101 rt:5 0000 0010 0100 1101 &cp2
228
+ CVM_MT_HSH_DATW14 010010 00101 rt:5 0000 0010 0100 1110 &cp2
229
+ CVM_MT_HSH_DATW15 010010 00101 rt:5 0000 0010 0100 1111 &cp2
230
+ CVM_MT_HSH_IVW0 010010 00101 rt:5 0000 0010 0101 0000 &cp2
231
+ CVM_MT_HSH_IVW1 010010 00101 rt:5 0000 0010 0101 0001 &cp2
232
+ CVM_MT_HSH_IVW2 010010 00101 rt:5 0000 0010 0101 0010 &cp2
233
+ CVM_MT_HSH_IVW3 010010 00101 rt:5 0000 0010 0101 0011 &cp2
234
+ CVM_MT_HSH_IVW4 010010 00101 rt:5 0000 0010 0101 0100 &cp2
235
+ CVM_MT_HSH_IVW5 010010 00101 rt:5 0000 0010 0101 0101 &cp2
236
+ CVM_MT_HSH_IVW6 010010 00101 rt:5 0000 0010 0101 0110 &cp2
237
+ CVM_MT_HSH_IVW7 010010 00101 rt:5 0000 0010 0101 0111 &cp2
238
CVM_MT_GFM_MUL0 010010 00101 rt:5 0000 0010 0101 1000 &cp2
239
CVM_MT_GFM_MUL1 010010 00101 rt:5 0000 0010 0101 1001 &cp2
240
CVM_MT_GFM_RESINP0 010010 00101 rt:5 0000 0010 0101 1010 &cp2
241
CVM_MT_GFM_RESINP1 010010 00101 rt:5 0000 0010 0101 1011 &cp2
242
+ CVM_MT_GFM_XOR0 010010 00101 rt:5 0000 0010 0101 1100 &cp2
243
CVM_MT_GFM_POLY 010010 00101 rt:5 0000 0010 0101 1110 &cp2
244
+ CVM_MT_SHA3_XORDAT0 010010 00101 rt:5 0000 0010 1100 0000 &cp2
245
+ CVM_MT_SHA3_XORDAT1 010010 00101 rt:5 0000 0010 1100 0001 &cp2
246
+ CVM_MT_SHA3_XORDAT2 010010 00101 rt:5 0000 0010 1100 0010 &cp2
247
+ CVM_MT_SHA3_XORDAT3 010010 00101 rt:5 0000 0010 1100 0011 &cp2
248
+ CVM_MT_SHA3_XORDAT4 010010 00101 rt:5 0000 0010 1100 0100 &cp2
249
+ CVM_MT_SHA3_XORDAT5 010010 00101 rt:5 0000 0010 1100 0101 &cp2
250
+ CVM_MT_SHA3_XORDAT6 010010 00101 rt:5 0000 0010 1100 0110 &cp2
251
+ CVM_MT_SHA3_XORDAT7 010010 00101 rt:5 0000 0010 1100 0111 &cp2
252
+ CVM_MT_SHA3_XORDAT8 010010 00101 rt:5 0000 0010 1100 1000 &cp2
253
+ CVM_MT_SHA3_XORDAT9 010010 00101 rt:5 0000 0010 1100 1001 &cp2
254
+ CVM_MT_SHA3_XORDAT10 010010 00101 rt:5 0000 0010 1100 1010 &cp2
255
+ CVM_MT_SHA3_XORDAT11 010010 00101 rt:5 0000 0010 1100 1011 &cp2
256
+ CVM_MT_SHA3_XORDAT12 010010 00101 rt:5 0000 0010 1100 1100 &cp2
257
+ CVM_MT_SHA3_XORDAT13 010010 00101 rt:5 0000 0010 1100 1101 &cp2
258
+ CVM_MT_SHA3_XORDAT14 010010 00101 rt:5 0000 0010 1100 1110 &cp2
259
+ CVM_MT_SHA3_XORDAT15 010010 00101 rt:5 0000 0010 1100 1111 &cp2
260
+ CVM_MT_SHA3_XORDAT16 010010 00101 rt:5 0000 0010 1101 0000 &cp2
261
+ CVM_MT_SHA3_XORDAT17 010010 00101 rt:5 0000 0010 1101 0001 &cp2
262
CVM_MT_CRC_LEN 010010 00101 rt:5 0001 0010 0000 0010 &cp2
263
CVM_MT_CRC_DWORD 010010 00101 rt:5 0001 0010 0000 0111 &cp2
264
CVM_MT_CRC_VAR 010010 00101 rt:5 0001 0010 0000 1000 &cp2
265
CVM_MT_CRC_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 0111 &cp2
266
CVM_MT_CRC_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 1000 &cp2
267
+ CVM_MT_HSH_STARTMD5 010010 00101 rt:5 0100 0000 0100 0111 &cp2
268
+ CVM_MT_HSH_STARTSHA256 010010 00101 rt:5 0100 0000 0100 1111 &cp2
269
+ CVM_MT_SHA3_STARTOP 010010 00101 rt:5 0100 0000 0101 0010 &cp2
270
+ CVM_MT_HSH_STARTSHA 010010 00101 rt:5 0100 0000 0101 0111 &cp2
271
CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 1101 &cp2
272
CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 0000 &cp2
273
CVM_MT_CRC_POLYNOMIAL_REFLECT 010010 00101 rt:5 0100 0010 0001 0000 &cp2
274
+ CVM_MT_HSH_STARTSHA512 010010 00101 rt:5 0100 0010 0100 1111 &cp2
275
CVM_MT_GFM_XORMUL1 010010 00101 rt:5 0100 0010 0101 1101 &cp2
276
]
277
CP2_Undef 010010 ----- ----- ---- ---- ---- ----
target/mips/tcg/octeon_translate.c
+102
@@ -47,6 +47,11 @@
47
#define CP2_MT_HELPER(NAME, SUFFIX) \
48
TRANS(NAME, trans_octeon_cp2_mt_helper, \
49
gen_helper_octeon_cp2_mt_ ## SUFFIX)
50
+#define CP2_MT_HELPER_ENV(NAME, SUFFIX) \
51
+ TRANS(NAME, trans_octeon_cp2_mt_helper_env, \
52
+ gen_helper_octeon_cp2_mt_ ## SUFFIX)
53
+#define CP2_MT_XOR_I64(NAME, FIELD) \
54
+ TRANS(NAME, trans_octeon_cp2_mt_xor_i64, OCTEON_CRYPTO_OFFSET(FIELD))
55
56
#define OCTEON_LO32_OFFSET (HOST_BIG_ENDIAN ? 4 : 0)
57
@@ -165,6 +170,19 @@ static bool trans_octeon_cp2_mt_hsh_pair(DisasContext *ctx, arg_cp2 *a,
170
return true;
171
}
172
173
+static bool trans_octeon_cp2_mt_xor_i64(DisasContext *ctx, arg_cp2 *a,
174
+ int offset)
175
+{
176
+ TCGv_i64 value = tcg_temp_new_i64();
177
+ TCGv_i64 old = tcg_temp_new_i64();
178
+
179
+ gen_load_gpr(value, a->rt);
180
+ tcg_gen_ld_i64(old, tcg_env, offset);
181
+ tcg_gen_xor_i64(old, old, value);
182
+ tcg_gen_st_i64(old, tcg_env, offset);
183
+ return true;
184
+}
185
+
186
static bool trans_octeon_cp2_mt_helper(DisasContext *ctx, arg_cp2 *a,
187
void (*gen_helper)(TCGv_env, TCGv_i64))
188
{
@@ -175,6 +193,13 @@ static bool trans_octeon_cp2_mt_helper(DisasContext *ctx, arg_cp2 *a,
193
return true;
194
}
195
196
+static bool trans_octeon_cp2_mt_helper_env(DisasContext *ctx, arg_cp2 *a,
197
+ void (*gen_helper)(TCGv_env))
198
+{
199
+ gen_helper(tcg_env);
200
+ return true;
201
+}
202
+
203
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT0, hsh_dat, 0);
204
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT1, hsh_dat, 1);
205
CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT2, hsh_dat, 2);
@@ -212,10 +237,35 @@ CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]);
237
CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly);
238
239
CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect);
240
+CP2_MF_I64(CVM_MF_SHA3_DAT24, sha3_dat24);
241
CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT0, gfm_mul_reflect0);
242
CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT1, gfm_mul_reflect1);
243
CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp_reflect0);
244
CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp_reflect1);
245
+CP2_MF_I64(CVM_MF_HSH_DATW0, hsh_dat[0]);
246
+CP2_MF_I64(CVM_MF_HSH_DATW1, hsh_dat[1]);
247
+CP2_MF_I64(CVM_MF_HSH_DATW2, hsh_dat[2]);
248
+CP2_MF_I64(CVM_MF_HSH_DATW3, hsh_dat[3]);
249
+CP2_MF_I64(CVM_MF_HSH_DATW4, hsh_dat[4]);
250
+CP2_MF_I64(CVM_MF_HSH_DATW5, hsh_dat[5]);
251
+CP2_MF_I64(CVM_MF_HSH_DATW6, hsh_dat[6]);
252
+CP2_MF_I64(CVM_MF_HSH_DATW7, hsh_dat[7]);
253
+CP2_MF_I64(CVM_MF_HSH_DATW8, hsh_dat[8]);
254
+CP2_MF_I64(CVM_MF_HSH_DATW9, hsh_dat[9]);
255
+CP2_MF_I64(CVM_MF_HSH_DATW10, hsh_dat[10]);
256
+CP2_MF_I64(CVM_MF_HSH_DATW11, hsh_dat[11]);
257
+CP2_MF_I64(CVM_MF_HSH_DATW12, hsh_dat[12]);
258
+CP2_MF_I64(CVM_MF_HSH_DATW13, hsh_dat[13]);
259
+CP2_MF_I64(CVM_MF_HSH_DATW14, hsh_dat[14]);
260
+CP2_MF_I64(CVM_MF_HSH_DATW15, hsh_dat[15]);
261
+CP2_MF_I64(CVM_MF_HSH_IVW0, hsh_iv[0]);
262
+CP2_MF_I64(CVM_MF_HSH_IVW1, hsh_iv[1]);
263
+CP2_MF_I64(CVM_MF_HSH_IVW2, hsh_iv[2]);
264
+CP2_MF_I64(CVM_MF_HSH_IVW3, hsh_iv[3]);
265
+CP2_MF_I64(CVM_MF_HSH_IVW4, hsh_iv[4]);
266
+CP2_MF_I64(CVM_MF_HSH_IVW5, hsh_iv[5]);
267
+CP2_MF_I64(CVM_MF_HSH_IVW6, hsh_iv[6]);
268
+CP2_MF_I64(CVM_MF_HSH_IVW7, hsh_iv[7]);
269
270
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT0, hsh_dat, 0);
271
CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT1, hsh_dat, 1);
@@ -254,11 +304,13 @@ CP2_MT_I64(CVM_MT_GFM_MUL0, gfm_mul[0]);
304
CP2_MT_I64(CVM_MT_GFM_MUL1, gfm_mul[1]);
305
CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]);
306
CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]);
307
+CP2_MT_XOR_I64(CVM_MT_GFM_XOR0, gfm_resinp[0]);
308
CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly);
309
CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf);
310
CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly);
311
312
CP2_MT_HELPER(CVM_MT_CRC_POLYNOMIAL_REFLECT, crc_write_polynomial_reflect);
313
+
314
CP2_MT_HELPER(CVM_MT_CRC_IV_REFLECT, crc_write_iv_reflect);
315
CP2_MT_HELPER(CVM_MT_CRC_BYTE, crc_write_byte);
316
CP2_MT_HELPER(CVM_MT_CRC_HALF, crc_write_half);
@@ -272,6 +324,56 @@ CP2_MT_HELPER(CVM_MT_CRC_DWORD_REFLECT, crc_write_dword_reflect);
324
CP2_MT_HELPER(CVM_MT_CRC_VAR_REFLECT, crc_write_var_reflect);
325
CP2_MT_HELPER(CVM_MT_GFM_XORMUL1_REFLECT, gfm_xormul1_reflect);
326
CP2_MT_HELPER(CVM_MT_GFM_XORMUL1, gfm_xormul1);
327
+CP2_MT_I64(CVM_MT_SHA3_DAT24, sha3_dat24);
328
+CP2_MT_I64(CVM_MT_SHA3_DAT15, hsh_dat[15]);
329
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT0, sha3_dat[0]);
330
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT1, sha3_dat[1]);
331
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT2, sha3_dat[2]);
332
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT3, sha3_dat[3]);
333
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT4, sha3_dat[4]);
334
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT5, sha3_dat[5]);
335
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT6, sha3_dat[6]);
336
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT7, sha3_dat[7]);
337
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT8, sha3_dat[8]);
338
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT9, sha3_dat[9]);
339
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT10, sha3_dat[10]);
340
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT11, sha3_dat[11]);
341
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT12, sha3_dat[12]);
342
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT13, sha3_dat[13]);
343
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT14, sha3_dat[14]);
344
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT15, sha3_dat[15]);
345
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT16, sha3_dat[16]);
346
+CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT17, sha3_dat[17]);
347
+CP2_MT_HELPER_ENV(CVM_MT_SHA3_STARTOP, sha3_startop);
348
+CP2_MT_HELPER(CVM_MT_HSH_STARTSHA1_COMPAT, hsh_startsha1_compat);
349
+CP2_MT_I64(CVM_MT_HSH_DATW0, hsh_dat[0]);
350
+CP2_MT_I64(CVM_MT_HSH_DATW1, hsh_dat[1]);
351
+CP2_MT_I64(CVM_MT_HSH_DATW2, hsh_dat[2]);
352
+CP2_MT_I64(CVM_MT_HSH_DATW3, hsh_dat[3]);
353
+CP2_MT_I64(CVM_MT_HSH_DATW4, hsh_dat[4]);
354
+CP2_MT_I64(CVM_MT_HSH_DATW5, hsh_dat[5]);
355
+CP2_MT_I64(CVM_MT_HSH_DATW6, hsh_dat[6]);
356
+CP2_MT_I64(CVM_MT_HSH_DATW7, hsh_dat[7]);
357
+CP2_MT_I64(CVM_MT_HSH_DATW8, hsh_dat[8]);
358
+CP2_MT_I64(CVM_MT_HSH_DATW9, hsh_dat[9]);
359
+CP2_MT_I64(CVM_MT_HSH_DATW10, hsh_dat[10]);
360
+CP2_MT_I64(CVM_MT_HSH_DATW11, hsh_dat[11]);
361
+CP2_MT_I64(CVM_MT_HSH_DATW12, hsh_dat[12]);
362
+CP2_MT_I64(CVM_MT_HSH_DATW13, hsh_dat[13]);
363
+CP2_MT_I64(CVM_MT_HSH_DATW14, hsh_dat[14]);
364
+CP2_MT_I64(CVM_MT_HSH_DATW15, hsh_dat[15]);
365
+CP2_MT_I64(CVM_MT_HSH_IVW0, hsh_iv[0]);
366
+CP2_MT_I64(CVM_MT_HSH_IVW1, hsh_iv[1]);
367
+CP2_MT_I64(CVM_MT_HSH_IVW2, hsh_iv[2]);
368
+CP2_MT_I64(CVM_MT_HSH_IVW3, hsh_iv[3]);
369
+CP2_MT_I64(CVM_MT_HSH_IVW4, hsh_iv[4]);
370
+CP2_MT_I64(CVM_MT_HSH_IVW5, hsh_iv[5]);
371
+CP2_MT_I64(CVM_MT_HSH_IVW6, hsh_iv[6]);
372
+CP2_MT_I64(CVM_MT_HSH_IVW7, hsh_iv[7]);
373
+CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5);
374
+CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256);
375
+CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha);
376
+CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512);
377
378
static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
379
{