fpu: Introduce FloatSNaNRule
Merge snan_bit_is_one and no_signaling_nans into one control. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson committed
May 1, 2026 at 14:19 UTC
acb6d598578fbb47b687ec02a664919950e15fbd
8 files changed
+51
-50
fpu/softfloat-specialize.c.inc
+18
-30
@@ -79,26 +79,6 @@ this code that are retained.
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* version 2 or later. See the COPYING file in the top-level directory.
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*/
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-/*
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- * Define whether architecture deviates from IEEE in not supporting
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- * signaling NaNs (so all NaNs are treated as quiet).
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- */
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-static inline bool no_signaling_nans(float_status *status)
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-{
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- return status->no_signaling_nans;
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-}
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-
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-/* Define how the architecture discriminates signaling NaNs.
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- * This done with the most significant bit of the fraction.
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- * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
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- * the msb must be zero. MIPS is (so far) unique in supporting both the
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- * 2008 revision and backward compatibility with their original choice.
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- */
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-static inline bool snan_bit_is_one(float_status *status)
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-{
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- return status->snan_bit_is_one;
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-}
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-
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/*----------------------------------------------------------------------------
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| For the deconstructed floating-point with fraction FRAC, return true
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| if the fraction represents a signalling NaN; otherwise false.
@@ -106,11 +86,15 @@ static inline bool snan_bit_is_one(float_status *status)
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static bool frac_msb_is_snan(bool msb, float_status *status)
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{
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- if (no_signaling_nans(status)) {
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+ switch (get_snan_rule(status)) {
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+ case float_snan_never:
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return false;
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- } else {
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- return msb == snan_bit_is_one(status);
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+ case float_snan_bit_is_one:
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+ return msb;
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+ case float_snan_bit_is_zero:
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+ return !msb;
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}
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+ g_assert_not_reached();
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}
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static bool parts_is_snan_frac(uint64_t frac, float_status *status)
@@ -172,14 +156,18 @@ FloatParts128 parts128_default_nan(float_status *status)
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static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
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{
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- g_assert(!no_signaling_nans(status));
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-
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- /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
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- if (snan_bit_is_one(status)) {
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+ switch (get_snan_rule(status)) {
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+ case float_snan_bit_is_zero:
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+ frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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+ break;
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+ case float_snan_bit_is_one:
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+ /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
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frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
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frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
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- } else {
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- frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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+ break;
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+ case float_snan_never:
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+ default:
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+ g_assert_not_reached();
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}
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return frac;
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}
@@ -390,7 +378,7 @@ bool floatx80_is_signaling_nan(floatx80 a, float_status *status)
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floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
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{
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/* None of the targets that have snan_bit_is_one use floatx80. */
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- assert(!snan_bit_is_one(status));
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+ assert(get_snan_rule(status) == float_snan_bit_is_zero);
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a.low |= UINT64_C(0xC000000000000000);
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return a;
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}
include/fpu/softfloat-helpers.h
+7
-7
@@ -127,14 +127,9 @@ static inline void set_default_nan_mode(bool val, float_status *status)
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status->default_nan_mode = val;
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}
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-static inline void set_snan_bit_is_one(bool val, float_status *status)
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+static inline void set_snan_rule(FloatSNaNRule val, float_status *status)
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{
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- status->snan_bit_is_one = val;
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-}
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-
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-static inline void set_no_signaling_nans(bool val, float_status *status)
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-{
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- status->no_signaling_nans = val;
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+ status->float_snan_rule = val;
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}
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static inline bool get_float_detect_tininess(const float_status *status)
@@ -203,6 +198,11 @@ static inline bool get_default_nan_mode(const float_status *status)
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return status->default_nan_mode;
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}
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+static inline FloatSNaNRule get_snan_rule(float_status *status)
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+{
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+ return status->float_snan_rule;
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+}
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+
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static inline FloatFTZDetection get_float_ftz_detection(const float_status *status)
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{
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return status->ftz_detection;
include/fpu/softfloat-types.h
+18
-7
@@ -192,6 +192,23 @@ typedef enum __attribute__((__packed__)) {
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floatx80_precision_s,
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} FloatX80RoundPrec;
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+/*
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+ * Define how the architecture discriminates signaling NaNs.
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+ * This done with the most significant bit of the fraction.
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+ *
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+ * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
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+ * the msb must be 0. But setting the msb to 1 got baked into HPPA, SH4,
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+ * and pre-2008 MIPS.
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+ *
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+ * Further, some architectures (or modes of architectures) do not detect
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+ * signaling NaNs at all.
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+ */
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+typedef enum __attribute__((__packed__)) {
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+ float_snan_bit_is_zero,
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+ float_snan_bit_is_one,
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+ float_snan_never,
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+} FloatSNaNRule;
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+
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/*
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* 2-input NaN propagation rule. Individual architectures have
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* different rules for which input NaN is propagated to the output
@@ -394,6 +411,7 @@ typedef struct float_status {
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Float2NaNPropRule float_2nan_prop_rule;
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Float3NaNPropRule float_3nan_prop_rule;
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FloatInfZeroNaNRule float_infzeronan_rule;
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+ FloatSNaNRule float_snan_rule;
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bool tininess_before_rounding;
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/* should denormalised results go to zero and set output_denormal_flushed? */
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bool flush_to_zero;
@@ -412,13 +430,6 @@ typedef struct float_status {
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* create a default NaN.
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*/
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uint8_t default_nan_pattern;
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- /*
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- * The flags below are not used on all specializations and may
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- * constant fold away (see snan_bit_is_one()/no_signalling_nans() in
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- * softfloat-specialize.inc.c)
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- */
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- bool snan_bit_is_one;
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- bool no_signaling_nans;
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/* should overflowed results subtract re_bias to its exponent? */
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bool rebias_overflow;
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/* should underflowed results add re_bias to its exponent? */
target/hppa/fpu_helper.c
+1
-1
@@ -66,7 +66,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
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set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
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/* Default NaN: sign bit clear, msb-1 frac bit set */
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set_float_default_nan_pattern(0b00100000, &env->fp_status);
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- set_snan_bit_is_one(true, &env->fp_status);
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+ set_snan_rule(float_snan_bit_is_one, &env->fp_status);
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/*
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* "PA-RISC 2.0 Architecture" says it is IMPDEF whether the flushing
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* enabled by FPSR.D happens before or after rounding. We pick "before"
target/mips/fpu_helper.h
+2
-1
@@ -35,7 +35,8 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
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* With nan2008, SNaNs are silenced in the usual way.
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* Before that, SNaNs are not silenced; default nans are produced.
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*/
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- set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
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+ set_snan_rule(nan2008 ? float_snan_bit_is_zero : float_snan_bit_is_one,
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+ &env->active_fpu.fp_status);
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set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
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/*
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* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
target/mips/msa.c
+2
-2
@@ -84,8 +84,8 @@ void msa_reset(CPUMIPSState *env)
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/* clear float_status nan mode */
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set_default_nan_mode(0, &env->active_tc.msa_fp_status);
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- /* set proper signanling bit meaning ("1" means "quiet") */
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- set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
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+ /* set proper signanling bit meaning */
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+ set_snan_rule(float_snan_bit_is_zero, &env->active_tc.msa_fp_status);
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/* Inf * 0 + NaN returns the input NaN */
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set_float_infzeronan_rule(float_infzeronan_dnan_never,
target/sh4/cpu.c
+1
-1
@@ -151,7 +151,7 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
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set_flush_to_zero(1, &env->fp_status);
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#endif
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set_default_nan_mode(1, &env->fp_status);
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- set_snan_bit_is_one(true, &env->fp_status);
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+ set_snan_rule(float_snan_bit_is_one, &env->fp_status);
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/* sign bit clear, set all frac bits other than msb */
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set_float_default_nan_pattern(0b00111111, &env->fp_status);
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/*
target/xtensa/cpu.c
+2
-1
@@ -209,7 +209,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
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#endif
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/* For inf * 0 + NaN, return the input NaN */
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set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
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- set_no_signaling_nans(!dfpu, &env->fp_status);
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+ set_snan_rule(dfpu ? float_snan_bit_is_zero : float_snan_never,
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+ &env->fp_status);
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/* Default NaN value: sign bit clear, set frac msb */
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set_float_default_nan_pattern(0b01000000, &env->fp_status);
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xtensa_use_first_nan(env, !dfpu);