@samitouri / QOSamiQemu / commits / acf74c1e8b

i386/cpu: Enable CPUID 0x1f & cache model for ClearwaterForest

ClearwaterForest has CPUID 0x1f by default, so force enabling this leaf for it (ClearwaterForect-v3). And add the cache model to ClearwaterForest (v3) to better emulate its environment. The cache model is based on ClearwaterForest-AP (Advanced Performance): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x0 (0) maximum IDs for cores in pkg = 0x3f (63) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0x8 (8) number of sets = 0x40 (64) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets (s) = 64 (size synth) = 32768 (32 KB) --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x0 (0) maximum IDs for cores in pkg = 0x3f (63) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0x8 (8) number of sets = 0x80 (128) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets (s) = 128 (size synth) = 65536 (64 KB) --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x7 (7) maximum IDs for cores in pkg = 0x3f (63) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0x10 (16) number of sets = 0x1000 (4096) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets (s) = 4096 (size synth) = 4194304 (4 MB) --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x3ff (1023) maximum IDs for cores in pkg = 0x3f (63) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0x10 (16) number of sets = 0x84000 (540672) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = true number of sets (s) = 540672 (size synth) = 553648128 (528 MB) --- cache 4 --- cache type = no more caches (0) Suggested-by: Zhijun Zeng <zhijun.zeng@intel.com> Suggested-by: Chao Peng <chao.p.peng@intel.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20260310140819.1563084-6-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Zhao Liu committed Mar 10, 2026 at 22:08 UTC acf74c1e8b91599ce330df9c86d3e944dc512ce4
1 file changed +94 -1
target/i386/cpu.c
+94 -1
@@ -3318,6 +3318,97 @@ static const CPUCaches xeon_srf_cache_info = {
3318 },
3319 };
3320
3321 +static const CPUCaches xeon_cwf_cache_info = {
3322 + .l1d_cache = &(CPUCacheInfo) {
3323 + /* CPUID 0x4.0x0.EAX */
3324 + .type = DATA_CACHE,
3325 + .level = 1,
3326 + .self_init = true,
3327 +
3328 + /* CPUID 0x4.0x0.EBX */
3329 + .line_size = 64,
3330 + .partitions = 1,
3331 + .associativity = 8,
3332 +
3333 + /* CPUID 0x4.0x0.ECX */
3334 + .sets = 64,
3335 +
3336 + /* CPUID 0x4.0x0.EDX */
3337 + .no_invd_sharing = false,
3338 + .inclusive = false,
3339 + .complex_indexing = false,
3340 +
3341 + .size = 32 * KiB,
3342 + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
3343 + },
3344 + .l1i_cache = &(CPUCacheInfo) {
3345 + /* CPUID 0x4.0x1.EAX */
3346 + .type = INSTRUCTION_CACHE,
3347 + .level = 1,
3348 + .self_init = true,
3349 +
3350 + /* CPUID 0x4.0x1.EBX */
3351 + .line_size = 64,
3352 + .partitions = 1,
3353 + .associativity = 8,
3354 +
3355 + /* CPUID 0x4.0x1.ECX */
3356 + .sets = 128,
3357 +
3358 + /* CPUID 0x4.0x1.EDX */
3359 + .no_invd_sharing = false,
3360 + .inclusive = false,
3361 + .complex_indexing = false,
3362 +
3363 + .size = 64 * KiB,
3364 + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
3365 + },
3366 + .l2_cache = &(CPUCacheInfo) {
3367 + /* CPUID 0x4.0x2.EAX */
3368 + .type = UNIFIED_CACHE,
3369 + .level = 2,
3370 + .self_init = true,
3371 +
3372 + /* CPUID 0x4.0x2.EBX */
3373 + .line_size = 64,
3374 + .partitions = 1,
3375 + .associativity = 16,
3376 +
3377 + /* CPUID 0x4.0x2.ECX */
3378 + .sets = 4096,
3379 +
3380 + /* CPUID 0x4.0x2.EDX */
3381 + .no_invd_sharing = false,
3382 + .inclusive = false,
3383 + .complex_indexing = false,
3384 +
3385 + .size = 4 * MiB,
3386 + .share_level = CPU_TOPOLOGY_LEVEL_MODULE,
3387 + },
3388 + .l3_cache = &(CPUCacheInfo) {
3389 + /* CPUID 0x4.0x3.EAX */
3390 + .type = UNIFIED_CACHE,
3391 + .level = 3,
3392 + .self_init = true,
3393 +
3394 + /* CPUID 0x4.0x3.EBX */
3395 + .line_size = 64,
3396 + .partitions = 1,
3397 + .associativity = 16,
3398 +
3399 + /* CPUID 0x4.0x3.ECX */
3400 + .sets = 540672,
3401 +
3402 + /* CPUID 0x4.0x3.EDX */
3403 + .no_invd_sharing = false,
3404 + .inclusive = false,
3405 + .complex_indexing = true,
3406 +
3407 + .size = 528 * MiB,
3408 + .share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
3409 + },
3410 +};
3411 +
3412 static const CPUCaches yongfeng_cache_info = {
3413 .l1d_cache = &(CPUCacheInfo) {
3414 /* CPUID 0x4.0x0.EAX */
@@ -5963,9 +6054,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
6054 },
6055 {
6056 .version = 3,
5966 - .note = "with its-no",
6057 + .note = "with its-no, cwf-ap cache model and 0x1f leaf",
6058 + .cache_info = &xeon_cwf_cache_info,
6059 .props = (PropValue[]) {
6060 { "its-no", "on" },
6061 + { "x-force-cpuid-0x1f", "on" },
6062 { /* end of list */ },
6063 }
6064 },