target/riscv: Fix size of irq_overflow_left
Fix to 64 bits to hold all relevant values. Also update comment to reflect that irq_overflow_left stores the ns beyond INT64_MAX until the next overflow, this to account for the uint64_t/int64_t timer value difference between RISCV/QEMU. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-17-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Johansson committed
May 20, 2026 at 14:53 UTC
ad8df5d448f55e40334f032f6bbb607ca7994dd2
1 file changed
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-2
target/riscv/cpu.h
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@@ -224,8 +224,8 @@ typedef struct PMUCTRState {
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uint64_t mhpmcounter_val;
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/* Snapshot value of a counter */
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uint64_t mhpmcounter_prev;
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- /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
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- target_ulong irq_overflow_left;
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+ /* Value beyond INT64_MAX before overflow interrupt trigger */
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+ uint64_t irq_overflow_left;
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} PMUCTRState;
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typedef struct PMUFixedCtrState {