hw/arm/tegra241-cmdqv: Initialize register state on reset
Initialize the Tegra241 CMDQV register state in the reset handler. Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Message-id: 20260609112552.378999-25-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Nicolin Chen committed
Jun 9, 2026 at 12:25 UTC
ae1a6a69c002fc331861be505d641014198bc33e
3 files changed
+42
hw/arm/tegra241-cmdqv.c
+38
@@ -863,6 +863,42 @@ free_viommu:
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return false;
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}
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+static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv)
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+{
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+ int i;
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+
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+ cmdqv->config = V_CONFIG_RESET;
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+ cmdqv->param = FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER);
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+ cmdqv->param = FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2,
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+ CMDQV_NUM_CMDQ_LOG2);
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+ cmdqv->param = FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VI_LOG2,
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+ CMDQV_NUM_SID_PER_VI_LOG2);
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+ trace_tegra241_cmdqv_init_regs(cmdqv->param);
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+ cmdqv->status = R_STATUS_CMDQV_ENABLED_MASK;
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+
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+ for (i = 0; i < 2; i++) {
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+ cmdqv->vi_err_map[i] = 0;
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+ cmdqv->vi_int_mask[i] = 0;
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+ }
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+ for (i = 0; i < 4; i++) {
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+ cmdqv->cmdq_err_map[i] = 0;
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+ cmdqv->vintf_cmdq_err_map[i] = 0;
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+ }
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+ cmdqv->vintf_config = 0;
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+ cmdqv->vintf_status = 0;
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+ for (i = 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) {
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+ cmdqv->cmdq_alloc_map[i] = 0;
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+ cmdqv->vcmdq_cons_indx[i] = 0;
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+ cmdqv->vcmdq_prod_indx[i] = 0;
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+ cmdqv->vcmdq_config[i] = 0;
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+ cmdqv->vcmdq_status[i] = 0;
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+ cmdqv->vcmdq_gerror[i] = 0;
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+ cmdqv->vcmdq_gerrorn[i] = 0;
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+ cmdqv->vcmdq_base[i] = 0;
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+ cmdqv->vcmdq_cons_indx_base[i] = 0;
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+ }
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+}
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+
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static void tegra241_cmdqv_reset(SMMUv3State *s)
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{
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Tegra241CMDQV *cmdqv = s->s_accel->cmdqv;
@@ -873,6 +909,8 @@ static void tegra241_cmdqv_reset(SMMUv3State *s)
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tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv);
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tegra241_cmdqv_free_all_vcmdq(cmdqv);
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+
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+ tegra241_cmdqv_init_regs(s, cmdqv);
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}
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static const MemoryRegionOps mmio_cmdqv_ops = {
hw/arm/tegra241-cmdqv.h
+3
@@ -89,6 +89,9 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8)
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FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8)
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FIELD(CONFIG, CONS_DRAM_EN, 20, 1)
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+/* CMDQV_EN=1, PER_CMD_OFFSET=16B, CLK_BATCH=256, CMD_BATCH=32. */
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+#define V_CONFIG_RESET 0x00020083
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+
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REG32(PARAM, 0x4)
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FIELD(PARAM, CMDQV_VER, 0, 4)
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FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4)
hw/arm/trace-events
+1
@@ -76,6 +76,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_id) "vS
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tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "offset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x"
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tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "offset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x"
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tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32_t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X"
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+tegra241_cmdqv_init_regs(uint32_t param) "register init, param=0x%08X"
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tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, const char *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x%"PRIx64" val: 0x%"PRIx64
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tegra241_cmdqv_read_vcmdq_page1(int index, const char *aperture, uint64_t offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64
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tegra241_cmdqv_write_vcmdq_page0(int index, const char *aperture, const char *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x%"PRIx64" val: 0x%"PRIx64