target/riscv: reject FMV.X.W/FMV.W.X under Zfinx
Zfinx explicitly excludes the FMV transfer instructions, but trans_fmv_x_w/trans_fmv_w_x used REQUIRE_ZFINX_OR_F so a Zfinx-only CPU accepted them. Require RVF instead so the transfers trap with an illegal instruction when only Zfinx is present. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4108 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn> Message-ID: <36c7cfebd27b4b6e8bcdd00e09e9dda0@wangyang25.otcaix.iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
wangyang committed
Aug 13, 2026 at 18:39 UTC
af1e669cef162e8d9b5f2f176e8b909d61c4b530
1 file changed
+4
-2
target/riscv/tcg/insn_trans/trans_rvf.c.inc
+4
-2
@@ -434,7 +434,8 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
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{
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/* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
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REQUIRE_FPU;
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- REQUIRE_ZFINX_OR_F(ctx);
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+ /* Zfinx explicitly excludes the FMV transfer instructions. */
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+ REQUIRE_EXT(ctx, RVF);
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -537,7 +538,8 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
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{
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/* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
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REQUIRE_FPU;
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- REQUIRE_ZFINX_OR_F(ctx);
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+ /* Zfinx explicitly excludes the FMV transfer instructions. */
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+ REQUIRE_EXT(ctx, RVF);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);