qemu-options.hx: Document arm-smmuv3 device's accel properties
Document arm-smmuv3 properties for setting HW-acceleration, Range Invalidation, and Address Translation Services support, as well as setting Output Address size and Substream ID size. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Tested-by: Shameer Kolothum <skolothumtho@nvidia.com> Signed-off-by: Nathan Chen <nathanc@nvidia.com> Message-id: 20260323182454.1416110-9-nathanc@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Nathan Chen committed
Mar 24, 2026 at 14:02 UTC
af35bc0c146ced44f6bfe98587495ae193adcec4
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qemu-options.hx
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@@ -1279,13 +1279,43 @@ SRST
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``aw-bits=val`` (val between 32 and 64, default depends on machine)
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This decides the address width of the IOVA address space.
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-``-device arm-smmuv3,primary-bus=id``
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+``-device arm-smmuv3,primary-bus=id[,option=...]``
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This is only supported by ``-machine virt`` (ARM).
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``primary-bus=id``
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Accepts either the default root complex (pcie.0) or a
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pxb-pcie based root complex.
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+ ``accel=on|off`` (default: off)
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+ Enables guest to leverage host SMMUv3 features for acceleration.
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+ Enabling accel configures the host SMMUv3 in nested mode to support
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+ vfio-pci passthrough.
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+
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+ The following options are available when accel=on.
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+ Note: 'auto' mode is not currently supported.
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+
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+ ``ril=on|off`` (default: on)
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+ Support for Range Invalidation, which allows the SMMUv3 driver to
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+ invalidate TLB entries for a range of IOVAs at once instead of issuing
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+ separate commands to invalidate each page. Must match with host SMMUv3
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+ Range Invalidation support.
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+
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+ ``ats=on|off`` (default: off)
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+ Support for Address Translation Services, which enables PCIe devices to
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+ cache address translations in their local TLB and reduce latency. Host
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+ SMMUv3 must support ATS in order to enable this feature for the vIOMMU.
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+
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+ ``oas=val`` (supported values are 44 and 48. default: 44)
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+ Sets the Output Address Size in bits. The value set here must be less
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+ than or equal to the host SMMUv3's supported OAS, so that the
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+ intermediate physical addresses (IPA) consumed by host SMMU for stage-2
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+ translation do not exceed the host's max supported IPA size.
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+
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+ ``ssidsize=val`` (val between 0 and 20. default: 0)
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+ Sets the Substream ID size in bits. When set to a non-zero value,
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+ PASID capability is advertised to the vIOMMU and accelerated use cases
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+ such as Shared Virtual Addressing (SVA) are supported.
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+
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``-device amd-iommu[,option=...]``
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Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU).
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Only available with ``-machine q35``, it supports the following options: