riscv: csr: do not drop C bit on misa write
According to spec: > Writing misa may increase IALIGN, e.g., by disabling the "C" extension. > If an instruction that would write misa increases IALIGN, and the > subsequent instruction’s address is not IALIGN-bit aligned, the > write to misa is suppressed, leaving misa unchanged. So attempt to disable C extension if next instruction is not aligned should not change the misa. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Vladimir Isaev <vvisaev@gmail.com> Reviewed-by: Chao Liu <chao.liu@processmission.com> Message-ID: <20260817150653.40357-2-vvisaev@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Vladimir Isaev committed
Aug 17, 2026 at 18:06 UTC
af37cd2821f970a1a9d2d34fa0d319f80d2ab84d
1 file changed
+7
-3
target/riscv/tcg/csr.c
+7
-3
@@ -2187,9 +2187,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
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/* Mask extensions that are not supported by this hart */
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val &= env->misa_ext_mask;
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- /* Suppress 'C' if next instruction is not aligned. */
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- if ((val & RVC) && (get_next_pc(env, ra) & 3) != 0) {
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- val &= ~RVC;
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+ /* drop write if RVC is cleared and next instruction is not aligned */
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+ if ((env->misa_ext & RVC) && !(val & RVC) &&
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+ (get_next_pc(env, ra) & 3) != 0) {
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+ qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value "
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+ "0x%x, MISA.C disable failed\n", env->misa_ext);
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+
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+ return RISCV_EXCP_NONE;
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}
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/* Disable RVG if any of its dependencies are disabled */