target/ppc: Move vector merge instructions to decodetree
Move below instructions to decodetree specification: vmrg{hb, hh, hw, lb, lh, lw} : VX-form The individual gen_vmrg* functions generated by GEN_VXFORM are replaced by a shared do_vmrg() helper dispatching to the existing gen_helper_VMRG* TCG helpers via the TRANS_FLAGS() macro, which also handles the ALTIVEC facility check. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Aboorva Devarajan <aboorvad@linux.ibm.com> Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Tested-by: Aniket Sahu <asahu1x@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-5-rathc@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Aboorva Devarajan committed
Aug 27, 2026 at 18:59 UTC
b0a1cc8d83c67a49496c97019f3008867184eae9
5 files changed
+40
-24
target/ppc/helper.h
+6
-6
@@ -173,12 +173,12 @@ DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
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DEF_HELPER_4(vcmpbfp_dot, void, env, avr, avr, avr)
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-DEF_HELPER_FLAGS_3(vmrglb, TCG_CALL_NO_RWG, void, avr, avr, avr)
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-DEF_HELPER_FLAGS_3(vmrglh, TCG_CALL_NO_RWG, void, avr, avr, avr)
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-DEF_HELPER_FLAGS_3(vmrglw, TCG_CALL_NO_RWG, void, avr, avr, avr)
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-DEF_HELPER_FLAGS_3(vmrghb, TCG_CALL_NO_RWG, void, avr, avr, avr)
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-DEF_HELPER_FLAGS_3(vmrghh, TCG_CALL_NO_RWG, void, avr, avr, avr)
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-DEF_HELPER_FLAGS_3(vmrghw, TCG_CALL_NO_RWG, void, avr, avr, avr)
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+DEF_HELPER_FLAGS_3(VMRGLB, TCG_CALL_NO_RWG, void, avr, avr, avr)
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+DEF_HELPER_FLAGS_3(VMRGLH, TCG_CALL_NO_RWG, void, avr, avr, avr)
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+DEF_HELPER_FLAGS_3(VMRGLW, TCG_CALL_NO_RWG, void, avr, avr, avr)
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+DEF_HELPER_FLAGS_3(VMRGHB, TCG_CALL_NO_RWG, void, avr, avr, avr)
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+DEF_HELPER_FLAGS_3(VMRGHH, TCG_CALL_NO_RWG, void, avr, avr, avr)
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+DEF_HELPER_FLAGS_3(VMRGHW, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(VMULESB, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(VMULESH, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(VMULESW, TCG_CALL_NO_RWG, void, avr, avr, avr)
target/ppc/insn32.decode
+9
@@ -795,6 +795,15 @@ VNOR 000100 ..... ..... ..... 10100000100 @VX
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VXOR 000100 ..... ..... ..... 10011000100 @VX
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VEQV 000100 ..... ..... ..... 11010000100 @VX
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+## Vector Merge Instructions
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+
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+VMRGHB 000100 ..... ..... ..... 00000001100 @VX
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+VMRGHH 000100 ..... ..... ..... 00001001100 @VX
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+VMRGHW 000100 ..... ..... ..... 00010001100 @VX
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+VMRGLB 000100 ..... ..... ..... 00100001100 @VX
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+VMRGLH 000100 ..... ..... ..... 00101001100 @VX
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+VMRGLW 000100 ..... ..... ..... 00110001100 @VX
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+
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## Vector Integer Average Instructions
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VAVGSB 000100 ..... ..... ..... 10100000010 @VX
target/ppc/int_helper.c
+6
-6
@@ -950,7 +950,7 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c,
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}
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#define VMRG_DO(name, element, access, ofs) \
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- void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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+ void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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{ \
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ppc_avr_t result; \
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int i, half = ARRAY_SIZE(r->element) / 2; \
@@ -963,11 +963,11 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c,
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}
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#define VMRG(suffix, element, access) \
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- VMRG_DO(mrgl##suffix, element, access, half) \
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- VMRG_DO(mrgh##suffix, element, access, 0)
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-VMRG(b, u8, VsrB)
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-VMRG(h, u16, VsrH)
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-VMRG(w, u32, VsrW)
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+ VMRG_DO(MRGL##suffix, element, access, half) \
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+ VMRG_DO(MRGH##suffix, element, access, 0)
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+VMRG(B, u8, VsrB)
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+VMRG(H, u16, VsrH)
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+VMRG(W, u32, VsrW)
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#undef VMRG_DO
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#undef VMRG
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target/ppc/translate/vmx-impl.c.inc
+19
-6
@@ -350,12 +350,25 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
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GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
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GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
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GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
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-GEN_VXFORM(vmrghb, 6, 0);
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-GEN_VXFORM(vmrghh, 6, 1);
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-GEN_VXFORM(vmrghw, 6, 2);
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-GEN_VXFORM(vmrglb, 6, 4);
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-GEN_VXFORM(vmrglh, 6, 5);
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-GEN_VXFORM(vmrglw, 6, 6);
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+
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+static bool do_vmrg(DisasContext *ctx, arg_VX *a,
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+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
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+{
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+ TCGv_ptr ra, rb, rd;
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+ REQUIRE_VECTOR(ctx);
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+ ra = gen_avr_ptr(a->vra);
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+ rb = gen_avr_ptr(a->vrb);
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+ rd = gen_avr_ptr(a->vrt);
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+ helper(rd, ra, rb);
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+ return true;
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+}
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+
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+TRANS_FLAGS(ALTIVEC, VMRGHB, do_vmrg, gen_helper_VMRGHB);
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+TRANS_FLAGS(ALTIVEC, VMRGHH, do_vmrg, gen_helper_VMRGHH);
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+TRANS_FLAGS(ALTIVEC, VMRGHW, do_vmrg, gen_helper_VMRGHW);
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+TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGLB);
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+TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH);
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+TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW);
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static void trans_vmrgew(DisasContext *ctx)
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{
target/ppc/translate/vmx-ops.c.inc
-6
@@ -33,12 +33,6 @@ GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
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GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
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GEN_VXFORM_300(bcds, 0, 27),
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-GEN_VXFORM(vmrghb, 6, 0),
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-GEN_VXFORM(vmrghh, 6, 1),
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-GEN_VXFORM(vmrghw, 6, 2),
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-GEN_VXFORM(vmrglb, 6, 4),
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-GEN_VXFORM(vmrglh, 6, 5),
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-GEN_VXFORM(vmrglw, 6, 6),
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GEN_VXFORM_300(vextublx, 6, 24),
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GEN_VXFORM_300(vextuhlx, 6, 25),
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GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),