Merge tag 'pull-target-arm-20260610' of https://gitlab.com/pm215/qemu into staging

target-arm queue: * Emulate various FP8 related features: FEAT_F8F16MM, FEAT_F8F32MM, FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2, FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4, FEAT_FP8FMA, FEAT_SSVE_FP8FMA, FEAT_SME_LUTv2, FEAT_FP8, FEAT_LUT * Emulate MTE4 features: FEAT_MTE_CANONICAL_TAGS, FEAT_MTE_NO_ADDRESS_TAGS, FEAT_MTE_PERM,FEAT_MTE_STORE_ONLY, FEAT_MTE_TAGGED_FAR * target/arm: fix WFET typo in syndrome * target/arm: Preparatory patches for implementing WFE * hw/dma/pl080: Don't use hw_error() for unimplemented features * hw/intc/exynos4210_combiner: Avoid hw_error for guest errors * hw/usb/hcd-ohci: Clean up USBPacket before freeing ISO TD packet * hw/core/qdev-clock: Fix potential null pointer dereference # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmopiZkZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vsMD/9+KuhMU13uZvmHrg3WVq2/ # BY1c0Z8mfB6fm0YfOtI9a4GpBKakwdJrsPcleKsJ8YIQHuaHcaSToqMAzZ97Iih8 # NmbPFtUmMWoMBA4CwpuiKkQdm7RgVbG0kafu6qcYBOP1f87jPQavjGC68zSijhEW # toRBEJtKRpPYl4ngbDtdmHbA3y4WA6ynNrCIvQHRFbqUX+GxRjPPNFpdHptEj+qo # cZiXQ0U2xNcCdtcio8hjWNtdyJ8fDt+4SvmTVa+6dwnmXx7Q4uC34YJ0619yN4JE # Ru2iLQnIAJvyhNtF+M2F0sitwMZA2CJ1VWZRmnRDbH9l7QwP2z/1raqaGIgm6E2s # Oia4QVGGuZTOxGJyJr/e9qUZZLhKZptLY/340QD7NpCQGkeefgmtKkoEcga93qnW # wYQD3t/tIG4xS8pdnbld4W1y5cCJ2Lg4kSDLxMbwrBv18gmsRxZdEHx4G1iVPnT6 # 5dGHEP81webn3sGgviPGGt4Bvp+1MQW0H4f53o0GVgdUN0rX4y1Z1AZa0j9tl9v1 # ifG6LWc09qsDkCsJB//xJ0ATT0ppWtbdIr7U5BJQjIaN5FNCXtZC2m3wDkKkfeqD # fBFAL+xYb9NoYXvDjTLZdBOvcXGZdeVJ0if4FPqHQuTD8DRq+Isbkmf/2pHteVPA # jjGHJKtkFAHXKCYAdgmXDg== # =q0nq # -----END PGP SIGNATURE----- # gpg: Signature made Wed 10 Jun 2026 11:58:17 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20260610' of https://gitlab.com/pm215/qemu: (71 commits) target/arm: Enable FEAT_F8F16MM for -cpu max target/arm: Implement FMMLA (FP8 to FP16) for SVE target/arm: Implement FMMLA (FP8 to FP16) for AdvSIMD target/arm: Enable FEAT_F8F32MM for -cpu max target/arm: Implement FMMLA (FP8 to FP32) for SVE target/arm: Implement FMMLA (FP8 to FP32) for AdvSIMD target/arm: Enable FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2 for -cpu max target/arm: Implement FDOT (FP8 to FP16) for SVE target/arm: Implement FDOT (FP8 to FP16) for AdvSIMD target/arm: Enable FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4 for -cpu max target/arm: Implement FDOT (FP8 to FP32) for SVE target/arm: Implement FDOT (FP8 to FP32) for AdvSIMD target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max target/arm: Implement FMLALL{BB,BT,TB,TT} for SVE target/arm: Implement FMLALL{BB, BT, TB, TT} for AdvSIMD target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE target/arm: Implement FMLALB, FMLALT for AdvSIMD target/arm: Enable FEAT_SME_LUTv2 for -cpu max target/arm: Implement LUTI4 (four registers, 8-bit) target/arm: Implement MOVT (vector to table) ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>