target/i386/mshv: migrate pending ints/excs
We use PENDING_INTERRUPTION, INTERRUPT_STATE, PENDING_EVENT hv registers to map and roundtrip from/to CPUX86State. We ignore HV_REGISTER_PENDING_EVENT1 which represent events for nested virt contexts, as we don't support nested virt with MSHV currently. Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20260417105618.3621-30-magnuskulke@linux.microsoft.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Magnus Kulke committed
Apr 17, 2026 at 12:56 UTC
b2c0cc6300f0a5fd1b5c69926565b6f9982962c2
3 files changed
+185
include/hw/hyperv/hvgdk_mini.h
+3
@@ -12,6 +12,9 @@
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typedef enum hv_register_name {
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/* Pending Interruption Register */
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HV_REGISTER_PENDING_INTERRUPTION = 0x00010002,
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+ HV_REGISTER_INTERRUPT_STATE = 0x00010003,
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+ HV_REGISTER_PENDING_EVENT0 = 0x00010004,
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+ HV_REGISTER_PENDING_EVENT1 = 0x00010005,
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/* X64 User-Mode Registers */
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HV_X64_REGISTER_RAX = 0x00020000,
include/system/mshv_int.h
+14
@@ -17,6 +17,20 @@
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#include "hw/hyperv/hvhdk.h"
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#define MSHV_MSR_ENTRIES_COUNT 64
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+
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+/*
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+ * Interruption-type encoding, used by the hypervisor in
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+ * hv_x64_pending_interruption_register.interruption_type
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+ * See TLFS 6.0 section 7.9.2, p55
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+ * https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/tlfs
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+ */
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+#define MSHV_HV_INTERRUPTION_TYPE_EXT_INT 0
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+#define MSHV_HV_INTERRUPTION_TYPE_NMI 2
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+#define MSHV_HV_INTERRUPTION_TYPE_HW_EXC 3
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+#define MSHV_HV_INTERRUPTION_TYPE_SW_INT 4
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+#define MSHV_HV_INTERRUPTION_TYPE_PRIV_SW_EXC 5
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+#define MSHV_HV_INTERRUPTION_TYPE_SW_EXC 6
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+
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#define MSHV_DIRTY_PAGES_BATCH_SIZE 0x10000
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typedef struct hyperv_message hv_message;
target/i386/mshv/mshv-cpu.c
+168
@@ -535,6 +535,164 @@ static int load_regs(CPUState *cpu)
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return 0;
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}
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+static int get_vcpu_events(CPUState *cpu)
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+{
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+ X86CPU *x86cpu = X86_CPU(cpu);
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+ CPUX86State *env = &x86cpu->env;
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+ struct hv_register_assoc assocs[] = {
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+ { .name = HV_REGISTER_PENDING_INTERRUPTION },
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+ { .name = HV_REGISTER_INTERRUPT_STATE },
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+ { .name = HV_REGISTER_PENDING_EVENT0 },
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+ };
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+ union hv_x64_pending_interruption_register pending_int;
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+ union hv_x64_interrupt_state_register int_state;
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+ union hv_x64_pending_exception_event pending_exc;
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+ int ret;
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+
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+ ret = mshv_get_generic_regs(cpu, assocs, ARRAY_SIZE(assocs));
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+ if (ret < 0) {
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+ error_report("failed to get vcpu event registers");
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+ return -1;
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+ }
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+
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+ pending_int.as_uint64 = assocs[0].value.reg64;
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+ int_state.as_uint64 = assocs[1].value.reg64;
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+ pending_exc = assocs[2].value.pending_exception_event;
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+
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+ /* Clear previous state. injected ints/excs are blanked w/ -1 */
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+ env->interrupt_injected = -1;
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+ env->soft_interrupt = 0;
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+ env->exception_injected = 0;
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+ env->exception_pending = 0;
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+ env->exception_nr = -1;
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+ env->has_error_code = 0;
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+ env->error_code = 0;
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+ env->exception_has_payload = 0;
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+ env->exception_payload = 0;
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+ env->nmi_injected = 0;
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+
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+ if (pending_int.interruption_pending) {
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+ switch (pending_int.interruption_type) {
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+ case MSHV_HV_INTERRUPTION_TYPE_EXT_INT:
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+ env->interrupt_injected = pending_int.interruption_vector;
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+ break;
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+ case MSHV_HV_INTERRUPTION_TYPE_NMI:
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+ env->nmi_injected = 1;
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+ break;
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+ case MSHV_HV_INTERRUPTION_TYPE_HW_EXC:
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+ env->exception_injected = 1;
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+ env->exception_nr = pending_int.interruption_vector;
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+ env->has_error_code = pending_int.deliver_error_code;
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+ env->error_code = pending_int.error_code;
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+ break;
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+ case MSHV_HV_INTERRUPTION_TYPE_SW_INT:
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+ env->interrupt_injected = pending_int.interruption_vector;
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+ env->soft_interrupt = 1;
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+ break;
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+ case MSHV_HV_INTERRUPTION_TYPE_SW_EXC:
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+ case MSHV_HV_INTERRUPTION_TYPE_PRIV_SW_EXC:
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+ env->exception_injected = 1;
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+ env->exception_nr = pending_int.interruption_vector;
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+ env->has_error_code = pending_int.deliver_error_code;
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+ env->error_code = pending_int.error_code;
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+ break;
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+ default:
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+ error_report("unknown interruption type %u",
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+ pending_int.interruption_type);
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+ return -EINVAL;
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+ }
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+ }
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+
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+ /* disabled for one instr after STI, MOV/POP SS, see hvf_store_events() */
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+ if (int_state.interrupt_shadow) {
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+ env->hflags |= HF_INHIBIT_IRQ_MASK;
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+ } else {
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+ env->hflags &= ~HF_INHIBIT_IRQ_MASK;
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+ }
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+
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+ /* see kvm_get_vcpu_events(), hvf_store_events() */
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+ if (int_state.nmi_masked) {
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+ env->hflags2 |= HF2_NMI_MASK;
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+ } else {
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+ env->hflags2 &= ~HF2_NMI_MASK;
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+ }
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+
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+ /* HV_REGISTER_PENDING_EVENT0: pending exception not yet injected */
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+ if (pending_exc.event_pending) {
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+ env->exception_pending = 1;
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+ env->exception_nr = pending_exc.vector;
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+ env->has_error_code = pending_exc.deliver_error_code;
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+ env->error_code = pending_exc.error_code;
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+ env->exception_has_payload = (pending_exc.exception_parameter != 0);
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+ env->exception_payload = pending_exc.exception_parameter;
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+ }
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+
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+ /*
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+ * Ignoring HV_REGISTER_PENDING_EVENT1, virtualization fault events, MSHV
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+ * does not support nested virtualization.
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+ */
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+
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+ return 0;
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+}
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+
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+static int set_vcpu_events(const CPUState *cpu)
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+{
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+ X86CPU *x86cpu = X86_CPU(cpu);
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+ CPUX86State *env = &x86cpu->env;
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+ union hv_x64_pending_interruption_register pending_int = { 0 };
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+ union hv_x64_interrupt_state_register int_state = { 0 };
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+ union hv_x64_pending_exception_event pending_exc = { 0 };
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+ struct hv_register_assoc assocs[3];
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+ int ret;
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+
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+ /* build pending_int from CPUX86State */
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+ if (env->exception_injected) {
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+ pending_int.interruption_pending = 1;
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+ pending_int.interruption_type = MSHV_HV_INTERRUPTION_TYPE_HW_EXC;
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+ pending_int.interruption_vector = env->exception_nr;
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+ pending_int.deliver_error_code = env->has_error_code;
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+ pending_int.error_code = env->error_code;
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+ } else if (env->nmi_injected) {
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+ pending_int.interruption_pending = 1;
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+ pending_int.interruption_type = MSHV_HV_INTERRUPTION_TYPE_NMI;
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+ pending_int.interruption_vector = EXCP02_NMI;
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+ } else if (env->interrupt_injected >= 0) {
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+ pending_int.interruption_pending = 1;
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+ pending_int.interruption_type = env->soft_interrupt
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+ ? MSHV_HV_INTERRUPTION_TYPE_SW_INT
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+ : MSHV_HV_INTERRUPTION_TYPE_EXT_INT;
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+ pending_int.interruption_vector = env->interrupt_injected;
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+ }
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+
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+ /* build int_state, normalize to bool */
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+ int_state.interrupt_shadow = !!(env->hflags & HF_INHIBIT_IRQ_MASK);
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+ int_state.nmi_masked = !!(env->hflags2 & HF2_NMI_MASK);
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+
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+ /* build pending_exc */
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+ if (env->exception_pending) {
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+ pending_exc.event_pending = 1;
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+ pending_exc.vector = env->exception_nr;
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+ pending_exc.deliver_error_code = env->has_error_code;
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+ pending_exc.error_code = env->error_code;
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+ pending_exc.exception_parameter = env->exception_payload;
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+ }
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+
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+ assocs[0].name = HV_REGISTER_PENDING_INTERRUPTION;
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+ assocs[0].value.reg64 = pending_int.as_uint64;
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+ assocs[1].name = HV_REGISTER_INTERRUPT_STATE;
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+ assocs[1].value.reg64 = int_state.as_uint64;
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+ assocs[2].name = HV_REGISTER_PENDING_EVENT0;
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+ assocs[2].value.pending_exception_event = pending_exc;
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+
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+ ret = mshv_set_generic_regs(cpu, assocs, ARRAY_SIZE(assocs));
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+ if (ret < 0) {
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+ error_report("failed to set vcpu event registers");
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+ return -1;
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+ }
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+
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+ return 0;
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+}
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+
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int mshv_arch_load_vcpu_state(CPUState *cpu)
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{
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int ret;
@@ -559,6 +717,11 @@ int mshv_arch_load_vcpu_state(CPUState *cpu)
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return ret;
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}
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+ ret = get_vcpu_events(cpu);
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+ if (ret < 0) {
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+ return ret;
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+ }
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+
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return 0;
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}
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@@ -1100,6 +1263,11 @@ int mshv_arch_store_vcpu_state(const CPUState *cpu)
1263
return ret;
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}
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+ ret = set_vcpu_events(cpu);
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+ if (ret < 0) {
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+ return ret;
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+ }
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+
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return 0;
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}
1273