@samitouri / QOSamiQemu / commits / b3a977da8f

target/arm: Only compile gicv5-cpuif.c when GICv5 is selected

Only compile gicv5-cpuif.c when ARM_GICV5 is Kconfig-selected, otherwise we get when building with --without-default-devices: Undefined symbols for architecture arm64: "_gicv5_activate", referenced from: _gicr_cdia_read in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_deactivate", referenced from: _gic_cddi_write in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_get_hppi", referenced from: _gic_hppi in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_request_config", referenced from: _gic_cdrcfg_write in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_set_enabled", referenced from: _gic_cddis_write in target_arm_tcg_gicv5-cpuif.c.o _gic_cden_write in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_set_handling", referenced from: _gic_cdhm_write in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_set_pending", referenced from: _gic_cdpend_write in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_set_priority", referenced from: _gic_cdpri_write in target_arm_tcg_gicv5-cpuif.c.o "_gicv5_set_target", referenced from: _gic_cdaff_write in target_arm_tcg_gicv5-cpuif.c.o Fixes: ee0f1ce00db ("target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns") Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260721122135.6288-4-philmd@oss.qualcomm.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Philippe Mathieu-Daudé committed Jul 27, 2026 at 10:28 UTC b3a977da8fc12f21f4674b433b9ff34d4ecb62ed
1 file changed +3
target/arm/tcg/meson.build
+3
@@ -91,6 +91,9 @@ arm_common_system_ss.add(files(
91 'tlb_helper.c',
92 'tlb-insns.c',
93 ))
94 +arm_common_system_ss.add(when: 'CONFIG_ARM_GICV5', if_true: files(
95 + 'gicv5-cpuif.c',
96 +))
97 arm_user_ss.add(files(
98 'tlb_helper.c',
99 ))