target/hexagon: Add imported macro, attr defs for sysemu
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Brian Cain committed
Jun 22, 2026 at 15:28 UTC
b3ac2be4990809f190f10487bc9ac45a46bbf2f8
2 files changed
+504
-13
target/hexagon/attribs_def.h.inc
+29
-6
@@ -52,6 +52,9 @@ DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "")
52
DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "")
53
DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
54
DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "")
55
+DEF_ATTRIB(CACHEOP, "Cache operation", "", "")
56
+DEF_ATTRIB(COPBYADDRESS, "Cache operation by address", "", "")
57
+DEF_ATTRIB(COPBYIDX, "Cache operation by index", "", "")
58
DEF_ATTRIB(RELEASE, "Releases a lock", "", "")
59
DEF_ATTRIB(ACQUIRE, "Acquires a lock", "", "")
60
@@ -101,7 +104,9 @@ DEF_ATTRIB(ROPS_3, "Compound instruction worth 3 RISC-ops", "", "")
104
105
/* access to implicit registers */
106
DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR")
107
+DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the program counter", "UREG.PC", "")
108
DEF_ATTRIB(IMPLICIT_WRITES_SP, "Writes the stack pointer", "", "UREG.SP")
109
+DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the stack pointer", "UREG.SP", "")
110
DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP")
111
DEF_ATTRIB(IMPLICIT_WRITES_LC0, "Writes loop count for loop 0", "", "UREG.LC0")
112
DEF_ATTRIB(IMPLICIT_WRITES_LC1, "Writes loop count for loop 1", "", "UREG.LC1")
@@ -111,13 +116,19 @@ DEF_ATTRIB(IMPLICIT_WRITES_P0, "Writes Predicate 0", "", "UREG.P0")
116
DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
117
DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
118
DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
114
-DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
115
-DEF_ATTRIB(IMPLICIT_READS_P0, "Reads the P0 register", "", "")
116
-DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "", "")
117
-DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
118
-DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
119
+DEF_ATTRIB(IMPLICIT_READS_P0, "Reads Predicate 0", "UREG.P0", "")
120
+DEF_ATTRIB(IMPLICIT_READS_P1, "Reads Predicate 1", "UREG.P1", "")
121
+DEF_ATTRIB(IMPLICIT_READS_P3, "Reads Predicate 3", "UREG.P3", "")
122
DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
120
-DEF_ATTRIB(IMPLICIT_READS_SP, "Reads the SP register", "", "")
123
+DEF_ATTRIB(IMPLICIT_WRITES_CCR, "Writes CCR register", "", "UREG.CCR")
124
+DEF_ATTRIB(IMPLICIT_WRITES_GOSP, "Writes GOSP register", "", "UREG.GOSP")
125
+DEF_ATTRIB(IMPLICIT_WRITES_SSR, "Writes SSR register", "", "UREG.SSR")
126
+DEF_ATTRIB(IMPLICIT_WRITES_SGP0, "Writes SGP0 register", "", "UREG.SGP0")
127
+DEF_ATTRIB(IMPLICIT_WRITES_SGP1, "Writes SGP1 register", "", "UREG.SGP1")
128
+DEF_ATTRIB(IMPLICIT_WRITES_IMASK_ANYTHREAD,
129
+ "Writes IMASK for any thread", "", "")
130
+DEF_ATTRIB(IMPLICIT_WRITES_STID_PRIO_ANYTHREAD,
131
+ "Writes STID priority for any thread", "", "")
132
DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
133
DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
134
DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
@@ -137,9 +148,14 @@ DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "")
148
DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "")
149
DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "")
150
DEF_ATTRIB(RESTRICT_PACKET_AXOK, "May exist with A-type or X-type", "", "")
151
+DEF_ATTRIB(RESTRICT_SLOT1_AOK, "Slot 1 is allowed", "", "")
152
153
DEF_ATTRIB(ICOP, "Instruction cache op", "", "")
154
155
+DEF_ATTRIB(EXCEPTION_SWI, "Software interrupt exception", "", "")
156
+DEF_ATTRIB(DMA, "DMA instruction", "", "")
157
+DEF_ATTRIB(NO_TIMING_LOG, "Does not get logged to the timing model", "", "")
158
+
159
DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "")
160
DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "")
161
DEF_ATTRIB(RET_TYPE, "return type", "", "")
@@ -151,6 +167,10 @@ DEF_ATTRIB(DCFETCH, "dcfetch type", "", "")
167
168
DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "")
169
170
+DEF_ATTRIB(DCTAGOP, "Data cache tag operation", "", "")
171
+DEF_ATTRIB(ICTAGOP, "Instruction cache tag operation", "", "")
172
+DEF_ATTRIB(L2TAGOP, "L2 cache tag operation", "", "")
173
+
174
DEF_ATTRIB(ICINVA, "icinva", "", "")
175
DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "")
176
@@ -166,6 +186,9 @@ DEF_ATTRIB(NOTE_LATEPRED, "The predicate can not be used as a .new", "", "")
186
DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "")
187
DEF_ATTRIB(NOTE_NOVP, "Cannot be paired with a HVX permute instruction", "", "")
188
DEF_ATTRIB(NOTE_VA_UNARY, "Combined with HVX ALU op (must be unary)", "", "")
189
+DEF_ATTRIB(NOTE_SLOT1_AOK, "Slot 1 is allowed", "", "")
190
+DEF_ATTRIB(NOTE_GUEST, "Guest mode instruction", "", "")
191
+DEF_ATTRIB(NOTE_BADTAG_UNDEF, "Bad tag results in undefined behavior", "", "")
192
193
/* V6 MMVector Notes for Documentation */
194
DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift resource.", "", "")
target/hexagon/imported/macros.def
+475
-7
@@ -353,6 +353,12 @@ DEF_MACRO(
353
()
354
)
355
356
+DEF_MACRO(
357
+ fREAD_SSR, /* read SSR register */
358
+ (READ_RREG(REG_SSR)), /* behavior */
359
+ ()
360
+)
361
+
362
DEF_MACRO(
363
fWRITE_LR, /* write lr */
364
WRITE_RREG(REG_LR,A), /* behavior */
@@ -371,12 +377,36 @@ DEF_MACRO(
377
(A_IMPLICIT_WRITES_SP)
378
)
379
380
+DEF_MACRO(
381
+ fWRITE_GOSP, /* write gosp */
382
+ WRITE_RREG(REG_GOSP,A), /* behavior */
383
+ (A_IMPLICIT_WRITES_GOSP)
384
+)
385
+
386
DEF_MACRO(
387
fREAD_SP, /* read stack pointer */
388
(READ_RREG(REG_SP)), /* behavior */
389
()
390
)
391
392
+DEF_MACRO(
393
+ fREAD_GOSP, /* read guest other stack pointer */
394
+ (READ_RREG(REG_GOSP)), /* behavior */
395
+ ()
396
+)
397
+
398
+DEF_MACRO(
399
+ fREAD_GELR, /* read guest other stack pointer */
400
+ (READ_RREG(REG_GELR)), /* behavior */
401
+ ()
402
+)
403
+
404
+DEF_MACRO(
405
+ fREAD_GEVB, /* read guest other stack pointer */
406
+ (READ_RREG(REG_GEVB)), /* behavior */
407
+ ()
408
+)
409
+
410
DEF_MACRO(
411
fREAD_CSREG, /* read CS register */
412
(READ_RREG(REG_CSA+N)), /* behavior */
@@ -570,6 +600,11 @@ DEF_MACRO(
600
WRITE_PREG(3,VAL), /* behavior */
601
(A_IMPLICIT_WRITES_P3)
602
)
603
+DEF_MACRO(
604
+ fWRITE_P3_LATE, /* write Predicate 0 */
605
+ {WRITE_PREG(3,VAL); fHIDE(MARK_LATE_PRED_WRITE(3))} , /* behavior */
606
+ (A_IMPLICIT_WRITES_P3,A_RESTRICT_LATEPRED)
607
+)
608
609
DEF_MACRO(
610
fPART1, /* write Predicate 0 */
@@ -660,6 +695,7 @@ DEF_MACRO(
695
((size8s_t)((size2s_t)(A))),
696
/* optional attributes */
697
)
698
+
699
DEF_MACRO(
700
fCAST2_8u, /* macro name */
701
((size8u_t)((size2u_t)(A))),
@@ -1532,18 +1568,137 @@ DEF_MACRO(fECHO,
1568
/* OS interface and stop/wait */
1569
/********************************************/
1570
1571
+DEF_MACRO(RUNNABLE_THREADS_MAX,
1572
+ /* */,
1573
+ ()
1574
+)
1575
+
1576
+DEF_MACRO(THREAD_IS_ON,
1577
+ ((PROC->arch_proc_options->thread_enable_mask>>TNUM) & 0x1),
1578
+ ()
1579
+)
1580
+
1581
+DEF_MACRO(THREAD_EN_MASK,
1582
+ ((PROC->arch_proc_options->thread_enable_mask)),
1583
+ ()
1584
+)
1585
+
1586
+
1587
+
1588
+DEF_MACRO(READ_IMASK,
1589
+ /* */,
1590
+ ()
1591
+)
1592
+DEF_MACRO(WRITE_IMASK,
1593
+ /* */,
1594
+ (A_IMPLICIT_WRITES_IMASK_ANYTHREAD)
1595
+)
1596
+
1597
+
1598
+DEF_MACRO(WRITE_PRIO,
1599
+ /* */,
1600
+ (A_IMPLICIT_WRITES_STID_PRIO_ANYTHREAD)
1601
+)
1602
+
1603
+
1604
+DEF_MACRO(DO_IASSIGNW,
1605
+ /* */,
1606
+ (A_IMPLICIT_WRITES_IMASK_ANYTHREAD)
1607
+)
1608
+
1609
+
1610
+
1611
+
1612
+DEF_MACRO(fDO_NMI,
1613
+ /* */,
1614
+)
1615
+
1616
+DEF_MACRO(fDO_TRACE,
1617
+ /* */,
1618
+)
1619
+
1620
+DEF_MACRO(DO_IASSIGNR,
1621
+ /* */,
1622
+ ()
1623
+)
1624
+
1625
+DEF_MACRO(DO_SWI,
1626
+ /* */,
1627
+ (A_EXCEPTION_SWI)
1628
+)
1629
+
1630
+DEF_MACRO(DO_CSWI,
1631
+ LOG_GLOBAL_REG_WRITE(REG_IPEND,GLOBAL_REG_READ(REG_IPEND) & ~((REG) & GLOBAL_REG_READ(REG_IEL)));,
1632
+ ()
1633
+)
1634
+
1635
+DEF_MACRO(DO_CIAD,
1636
+ sys_ciad(thread,VAL); LOG_GLOBAL_REG_WRITE(REG_IAD,GLOBAL_REG_READ(REG_IAD) & ~(VAL));,
1637
+ (A_EXCEPTION_SWI)
1638
+)
1639
+
1640
+DEF_MACRO(DO_SIAD,
1641
+ sys_siad(thread,VAL); LOG_GLOBAL_REG_WRITE(REG_IAD,GLOBAL_REG_READ(REG_IAD) | (VAL));,
1642
+ (A_EXCEPTION_SWI)
1643
+)
1644
+
1645
+DEF_MACRO(fBREAK,
1646
+ /* */,
1647
+ ()
1648
+)
1649
+
1650
DEF_MACRO(fPAUSE,
1651
{sys_pause(thread, insn->slot, IMM);},
1652
()
1653
)
1654
1655
+
1656
DEF_MACRO(fTRAP,
1541
- warn("Trap NPC=%x ",fREAD_NPC());
1542
- warn("Trap exception, PCYCLE=%lld TYPE=%d NPC=%x IMM=0x%x",thread->processor_ptr->pstats[pcycles],TRAPTYPE,fREAD_NPC(),IMM);
1543
- register_trap_exception(thread,fREAD_NPC(),TRAPTYPE,IMM);,
1657
+ /* */,
1658
+ (A_EXCEPTION_SWI)
1659
+)
1660
+
1661
+DEF_MACRO(fCLEAR_RTE_EX,
1662
+ /* */,
1663
+ ()
1664
+)
1665
+
1666
+DEF_MACRO(fTLB_LOCK_AVAILABLE,
1667
+ (fREAD_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_TLBLOCK) == 0),
1668
+ ()
1669
+)
1670
+
1671
+DEF_MACRO(fK0_LOCK_AVAILABLE,
1672
+ (fREAD_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_K0LOCK) == 0),
1673
()
1674
)
1675
1676
+DEF_MACRO(fSET_TLB_LOCK,
1677
+ {
1678
+ if (fTLB_LOCK_AVAILABLE()) {
1679
+ fLOG_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_TLBLOCK,1);
1680
+ } else {
1681
+ sys_waiting_for_tlb_lock(thread);
1682
+ }
1683
+ },
1684
+ ()
1685
+)
1686
+
1687
+DEF_MACRO(fSET_K0_LOCK,
1688
+ /* */,
1689
+ ()
1690
+)
1691
+
1692
+DEF_MACRO(fCLEAR_TLB_LOCK,
1693
+ /* */,
1694
+ ()
1695
+)
1696
+
1697
+DEF_MACRO(fCLEAR_K0_LOCK,
1698
+ /* */,
1699
+ ()
1700
+)
1701
+
1702
DEF_MACRO(fALIGN_REG_FIELD_VALUE,
1703
((VAL)<<reg_field_info[FIELD].offset),
1704
/* */
@@ -1554,6 +1709,24 @@ DEF_MACRO(fGET_REG_FIELD_MASK,
1709
/* */
1710
)
1711
1712
+DEF_MACRO(fLOG_REG_FIELD,
1713
+ LOG_MASKED_REG_WRITE(thread,REG_##REG,
1714
+ fALIGN_REG_FIELD_VALUE(FIELD,VAL),
1715
+ fGET_REG_FIELD_MASK(FIELD)),
1716
+ ()
1717
+)
1718
+
1719
+DEF_MACRO(fWRITE_GLOBAL_REG_FIELD,
1720
+ /* */,
1721
+)
1722
+
1723
+DEF_MACRO(fLOG_GLOBAL_REG_FIELD,
1724
+ LOG_MASKED_GLOBAL_REG_WRITE(REG_##REG,
1725
+ fALIGN_REG_FIELD_VALUE(FIELD,VAL),
1726
+ fGET_REG_FIELD_MASK(FIELD)),
1727
+ ()
1728
+)
1729
+
1730
DEF_MACRO(fREAD_REG_FIELD,
1731
fEXTRACTU_BITS(thread->Regs[REG_##REG],
1732
reg_field_info[FIELD].width,
@@ -1561,6 +1734,11 @@ DEF_MACRO(fREAD_REG_FIELD,
1734
/* ATTRIBS */
1735
)
1736
1737
+DEF_MACRO(fREAD_GLOBAL_REG_FIELD,
1738
+ /* */,
1739
+ /* ATTRIBS */
1740
+)
1741
+
1742
DEF_MACRO(fGET_FIELD,
1743
fEXTRACTU_BITS(VAL,
1744
reg_field_info[FIELD].width,
@@ -1576,6 +1754,174 @@ DEF_MACRO(fSET_FIELD,
1754
/* ATTRIBS */
1755
)
1756
1757
+DEF_MACRO(fSET_RUN_MODE_NOW,
1758
+ /* */,
1759
+)
1760
+
1761
+DEF_MACRO(fIN_DEBUG_MODE,
1762
+ (thread->debug_mode || (fREAD_GLOBAL_REG_FIELD(ISDBST,ISDBST_DEBUGMODE) & 1<<TNUM)),
1763
+ ()
1764
+)
1765
+DEF_MACRO(fIN_DEBUG_MODE_NO_ISDB,
1766
+ (thread->debug_mode),
1767
+ ()
1768
+)
1769
+
1770
+
1771
+DEF_MACRO(fIN_DEBUG_MODE_WARN,
1772
+ {
1773
+ if (fREAD_GLOBAL_REG_FIELD(ISDBST,ISDBST_DEBUGMODE) & 1<<TNUM)
1774
+ warn("In ISDB debug mode, but TB told me to step normally");
1775
+ },
1776
+ ()
1777
+)
1778
+
1779
+DEF_MACRO(fCLEAR_RUN_MODE,
1780
+ {fLOG_GLOBAL_REG_FIELD(MODECTL,MODECTL_E,
1781
+ fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_E) & ~(1<<(TNUM)))},
1782
+ /* NOTHING */
1783
+)
1784
+
1785
+DEF_MACRO(fCLEAR_RUN_MODE_NOW,
1786
+ /* */,
1787
+ /* NOTHING */
1788
+)
1789
+
1790
+DEF_MACRO(fGET_RUN_MODE,
1791
+ /* */,
1792
+)
1793
+
1794
+DEF_MACRO(fSET_WAIT_MODE,
1795
+ {fLOG_GLOBAL_REG_FIELD(MODECTL,MODECTL_W,
1796
+ fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_W) | 1<<(TNUM))},
1797
+ /* NOTHING */
1798
+)
1799
+
1800
+DEF_MACRO(fCLEAR_WAIT_MODE,
1801
+ /* */,
1802
+)
1803
+
1804
+DEF_MACRO(fGET_WAIT_MODE,
1805
+ /* */,
1806
+)
1807
+
1808
+
1809
+DEF_MACRO(fRESET_THREAD,
1810
+ register_reset_interrupt(T,NUM),
1811
+)
1812
+
1813
+DEF_MACRO(fREAD_CURRENT_EVB,
1814
+ (GLOBAL_REG_READ(REG_EVB)),
1815
+ /* nothing */
1816
+)
1817
+
1818
+DEF_MACRO(fREAD_ELR,
1819
+ READ_RREG(REG_ELR),
1820
+ ()
1821
+)
1822
+
1823
+DEF_MACRO(fPOW2_HELP_ROUNDUP,
1824
+ ((VAL) | ((VAL) >> 1) | ((VAL) >> 2) | ((VAL) >> 4) | ((VAL) >> 8) | ((VAL) >> 16)),
1825
+ ()
1826
+)
1827
+
1828
+DEF_MACRO(fPOW2_ROUNDUP,
1829
+ fPOW2_HELP_ROUNDUP((VAL)-1)+1,
1830
+ ()
1831
+)
1832
+
1833
+DEF_MACRO(fTLB_IDXMASK,
1834
+ /* */,
1835
+ ()
1836
+)
1837
+
1838
+DEF_MACRO(fTLB_NONPOW2WRAP,
1839
+ /* */,
1840
+ /* ATTRIBS */
1841
+)
1842
+
1843
+DEF_MACRO(fTLBW,
1844
+ /* */,
1845
+ /* ATTRIBS */
1846
+)
1847
+
1848
+DEF_MACRO(fTLB_ENTRY_OVERLAP,
1849
+ fHIDE( (sys_check_overlap(thread,VALUE)!=-2) ),
1850
+ /* ATTRIBS */
1851
+)
1852
+
1853
+DEF_MACRO(fTLB_ENTRY_OVERLAP_IDX,
1854
+ fHIDE(sys_check_overlap(thread,VALUE)),
1855
+ /* ATTRIBS */
1856
+)
1857
+
1858
+
1859
+DEF_MACRO(fTLBR,
1860
+ TLB_REG_READ(fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX))),
1861
+ /* ATTRIBS */
1862
+)
1863
+
1864
+DEF_MACRO(fTLBP,
1865
+ tlb_lookup(thread,((TLBHI)>>12),((TLBHI)<<12),1),
1866
+ /* attribs */
1867
+)
1868
+
1869
+
1870
+
1871
+DEF_MACRO(READ_SGP0,
1872
+ READ_RREG(REG_SGP),
1873
+ ()
1874
+)
1875
+
1876
+DEF_MACRO(READ_SGP1,
1877
+ READ_RREG(REG_SGP+1),
1878
+ ()
1879
+)
1880
+
1881
+DEF_MACRO(READ_SGP10,
1882
+ READ_RREG_PAIR(REG_SGP),
1883
+ ()
1884
+)
1885
+
1886
+DEF_MACRO(READ_UGP,
1887
+ READ_RREG(REG_UGP),
1888
+)
1889
+
1890
+DEF_MACRO(WRITE_SGP0,
1891
+ WRITE_RREG(REG_SGP,VAL),
1892
+ (A_IMPLICIT_WRITES_SGP0)
1893
+)
1894
+
1895
+DEF_MACRO(WRITE_SGP1,
1896
+ WRITE_RREG(REG_SGP+1,VAL),
1897
+ (A_IMPLICIT_WRITES_SGP1)
1898
+)
1899
+
1900
+DEF_MACRO(WRITE_SGP10,
1901
+ WRITE_RREG_PAIR(REG_SGP,VAL),
1902
+ (A_IMPLICIT_WRITES_SGP0,A_IMPLICIT_WRITES_SGP1)
1903
+)
1904
+
1905
+DEF_MACRO(WRITE_UGP,
1906
+ WRITE_RREG(REG_UGP,VAL),
1907
+)
1908
+
1909
+DEF_MACRO(fSTART,
1910
+ /* */,
1911
+ ()
1912
+)
1913
+
1914
+DEF_MACRO(fRESUME,
1915
+ fLOG_GLOBAL_REG_FIELD(MODECTL,MODECTL_W,
1916
+ fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_W) & (~(REG))),
1917
+ ()
1918
+)
1919
+
1920
+DEF_MACRO(fGET_TNUM,
1921
+ thread->threadId,
1922
+ ()
1923
+)
1924
+
1925
/********************************************/
1926
/* Cache Management */
1927
/********************************************/
@@ -1602,19 +1948,49 @@ DEF_MACRO(fISYNC,
1948
)
1949
1950
1951
+DEF_MACRO(fICFETCH,
1952
+ ,
1953
+ ()
1954
+)
1955
+
1956
DEF_MACRO(fDCFETCH,
1957
sys_dcfetch(thread, (REG), insn->slot),
1958
(A_MEMLIKE)
1959
)
1960
1961
DEF_MACRO(fICINVA,
1611
- {
1612
- arch_internal_flush(thread->processor_ptr, 0, 0xffffffff);
1613
- sys_icinva(thread, (REG),insn->slot);
1614
- },
1962
+ /* */,
1963
(A_ICINVA)
1964
)
1965
1966
+DEF_MACRO(fDCTAGR,
1967
+ ({DST=sys_dctagr(thread, INDEX, insn->slot,DSTREGNO);})/* FIXME */,
1968
+ ()
1969
+)
1970
+
1971
+DEF_MACRO(fDCTAGW,
1972
+ (sys_dctagw(thread, INDEX, PART2, insn->slot)),
1973
+ ()
1974
+)
1975
+DEF_MACRO(fICTAGR,
1976
+ ({DST=sys_ictagr(thread, INDEX, insn->slot,REGNO);}),
1977
+ ()
1978
+)
1979
+
1980
+DEF_MACRO(fICDATAR,
1981
+ ({DST=sys_icdatar(thread, INDEX, insn->slot);}),
1982
+ ()
1983
+)
1984
+
1985
+DEF_MACRO(fICTAGW,
1986
+ (sys_ictagw(thread, INDEX, PART2, insn->slot)),
1987
+ ()
1988
+)
1989
+DEF_MACRO(fICDATAW,
1990
+ ({ fHIDE(); }),
1991
+ ()
1992
+)
1993
+
1994
DEF_MACRO(fL2FETCH,
1995
sys_l2fetch(thread, ADDR,HEIGHT,WIDTH,STRIDE,FLAGS, insn->slot),
1996
(A_MEMLIKE,A_L2FETCH)
@@ -1635,6 +2011,12 @@ DEF_MACRO(fDCZEROA,
2011
(A_MEMLIKE)
2012
)
2013
2014
+DEF_MACRO(fDCINVA,
2015
+ sys_dcinva(thread, (REG)),
2016
+ (A_MEMLIKE)
2017
+)
2018
+
2019
+
2020
DEF_MACRO(fCHECKFORPRIV,
2021
{sys_check_privs(thread); if (EXCEPTION_DETECTED) return; },
2022
()
@@ -1645,6 +2027,16 @@ DEF_MACRO(fCHECKFORGUEST,
2027
()
2028
)
2029
2030
+DEF_MACRO(fTAKEN_INTERRUPT_EDGECLEAR,
2031
+ { proc->global_regs[REG_IPEND] &= ~(INT_NUMTOMASK(intnum) & proc->global_regs[REG_IEL]); },
2032
+ ()
2033
+)
2034
+
2035
+DEF_MACRO(fSET_IAD,
2036
+ /* */,
2037
+ ()
2038
+)
2039
+
2040
DEF_MACRO(fBRANCH_SPECULATE_STALL,
2041
{
2042
sys_speculate_branch_stall(thread, insn->slot, JUMP_COND(JUMP_PRED_SET),
@@ -1664,3 +2056,79 @@ DEF_MACRO(IV1DEAD,
2056
,
2057
()
2058
)
2059
+
2060
+DEF_MACRO(fIN_MONITOR_MODE,
2061
+ sys_in_monitor_mode(thread),
2062
+ ()
2063
+)
2064
+
2065
+DEF_MACRO(fIN_USER_MODE,
2066
+ sys_in_user_mode(thread),
2067
+ ()
2068
+)
2069
+
2070
+DEF_MACRO(fIN_GUEST_MODE,
2071
+ sys_in_guest_mode(thread),
2072
+ ()
2073
+)
2074
+
2075
+DEF_MACRO(fGRE_ENABLED,
2076
+ fREAD_REG_FIELD(CCR,CCR_GRE),
2077
+ ()
2078
+)
2079
+
2080
+DEF_MACRO(fGTE_ENABLED,
2081
+ fREAD_REG_FIELD(CCR,CCR_GRE),
2082
+ ()
2083
+)
2084
+
2085
+DEF_MACRO(fTRAP1_VIRTINSN,
2086
+ ((fIN_GUEST_MODE())
2087
+ && (fGRE_ENABLED())
2088
+ && ( ((IMM) == 1)
2089
+ || ((IMM) == 3)
2090
+ || ((IMM) == 4)
2091
+ || ((IMM) == 6))),
2092
+ ()
2093
+)
2094
+
2095
+DEF_MACRO(fVIRTINSN_RTE,
2096
+ do {
2097
+ thread->trap1_info = TRAP1_VIRTINSN_RTE;
2098
+ fLOG_REG_FIELD(SSR,SSR_SS,fREAD_REG_FIELD(GSR,GSR_SS));
2099
+ fLOG_REG_FIELD(CCR,CCR_GIE,fREAD_REG_FIELD(GSR,GSR_IE));
2100
+ fLOG_REG_FIELD(SSR,SSR_GM,!fREAD_REG_FIELD(GSR,GSR_UM));
2101
+ fBRANCH((fREAD_GELR() & -4),COF_TYPE_RTE);
2102
+ fINTERNAL_CLEAR_SAMEPAGE();
2103
+ } while (0),
2104
+ (A_IMPLICIT_WRITES_CCR,A_IMPLICIT_WRITES_SSR)
2105
+)
2106
+
2107
+DEF_MACRO(fVIRTINSN_SETIE,
2108
+ do {
2109
+ fLOG_REG_FIELD(CCR,CCR_GIE,(REG) & 1);
2110
+ REG = fREAD_REG_FIELD(CCR,CCR_GIE);
2111
+ thread->trap1_info = TRAP1_VIRTINSN_SETIE;
2112
+ } while (0),
2113
+ (A_IMPLICIT_WRITES_CCR)
2114
+)
2115
+
2116
+DEF_MACRO(fVIRTINSN_GETIE,
2117
+ {
2118
+ thread->trap1_info = TRAP1_VIRTINSN_GETIE;
2119
+ REG = fREAD_REG_FIELD(CCR,CCR_GIE);
2120
+ },
2121
+ ()
2122
+)
2123
+
2124
+DEF_MACRO(fVIRTINSN_SPSWAP,
2125
+ do {
2126
+ if (fREAD_REG_FIELD(GSR,GSR_UM)) {
2127
+ size4u_t TEMP = REG;
2128
+ REG = fREAD_GOSP();
2129
+ fWRITE_GOSP(TEMP);
2130
+ thread->trap1_info = TRAP1_VIRTINSN_SPSWAP;
2131
+ }
2132
+ } while (0),
2133
+ (A_IMPLICIT_WRITES_GOSP)
2134
+)