tests/qtest: pca9554: test the PCA9536 4-bit variant
The PCA9536 shares the PCA9554 register map and code path but exposes only four pins. Add a pca9536 node and check its reset defaults and output-to-input reflection are masked to the low nibble. Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260709-catalina-upgrade-v1-23-82a63fead90c@free.fr Signed-off-by: Cédric Le Goater <clg@redhat.com>
Emmanuel Blot committed
Jul 9, 2026 at 17:23 UTC
b3fa8825086dcf217ea34dd1073cfd2fc0a790c2
1 file changed
+70
tests/qtest/pca9554-test.c
+70
@@ -129,6 +129,66 @@ static void test_no_autoincrement(void *obj, void *data,
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g_assert_cmphex(i2c_get8(dev, PCA9554_POLARITY), ==, 0x33);
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}
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+/*
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+ * The PCA9536 shares the PCA9554 register map but only has four pins, so its
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+ * reset defaults and pin logic are masked to the low nibble.
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+ */
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+static void test_pca9536_reset_defaults(void *obj, void *data,
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+ QGuestAllocator *alloc)
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+{
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+ QI2CDevice *dev = (QI2CDevice *)obj;
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+
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x0F);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_OUTPUT), ==, 0x0F);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_POLARITY), ==, 0x00);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_CONFIG), ==, 0x0F);
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+}
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+
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+/* Only the four low pins are driven; the upper nibble stays low. */
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+static void test_pca9536_output_drives_input(void *obj, void *data,
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+ QGuestAllocator *alloc)
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+{
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+ QI2CDevice *dev = (QI2CDevice *)obj;
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+
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+ i2c_set8(dev, PCA9554_CONFIG, 0x00);
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+
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+ i2c_set8(dev, PCA9554_OUTPUT, 0x0A);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x0A);
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+
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+ i2c_set8(dev, PCA9554_OUTPUT, 0x00);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x00);
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+}
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+
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+/*
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+ * The four upper bits address pins that do not exist on the PCA9536, so writes
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+ * to the register map discard them: the writable registers read back with bits
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+ * [7:4] cleared, and driving them onto the pins never surfaces in INPUT.
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+ */
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+static void test_pca9536_ignores_upper_bits(void *obj, void *data,
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+ QGuestAllocator *alloc)
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+{
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+ QI2CDevice *dev = (QI2CDevice *)obj;
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+
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+ /* Bits [7:4] are dropped on write; bits [3:0] survive. */
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+ i2c_set8(dev, PCA9554_OUTPUT, 0xFA);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_OUTPUT), ==, 0x0A);
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+
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+ i2c_set8(dev, PCA9554_POLARITY, 0xF5);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_POLARITY), ==, 0x05);
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+
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+ i2c_set8(dev, PCA9554_CONFIG, 0xF3);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_CONFIG), ==, 0x03);
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+
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+ /*
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+ * With all four pins as outputs, driving 0xFF only affects the low
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+ * nibble.
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+ */
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+ i2c_set8(dev, PCA9554_POLARITY, 0x00);
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+ i2c_set8(dev, PCA9554_CONFIG, 0x00);
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+ i2c_set8(dev, PCA9554_OUTPUT, 0xFF);
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+ g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x0F);
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+}
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+
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static void pca9554_register_nodes(void)
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{
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QOSGraphEdgeOptions opts = {
@@ -148,6 +208,16 @@ static void pca9554_register_nodes(void)
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qos_add_test("polarity-with-output", "pca9554", test_polarity_with_output,
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NULL);
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qos_add_test("no-autoincrement", "pca9554", test_no_autoincrement, NULL);
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+
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+ qos_node_create_driver("pca9536", i2c_device_create);
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+ qos_node_consumes("pca9536", "i2c-bus", &opts);
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+
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+ qos_add_test("reset-defaults", "pca9536", test_pca9536_reset_defaults,
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+ NULL);
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+ qos_add_test("output-drives-input", "pca9536",
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+ test_pca9536_output_drives_input, NULL);
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+ qos_add_test("ignores-upper-bits", "pca9536",
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+ test_pca9536_ignores_upper_bits, NULL);
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}
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libqos_init(pca9554_register_nodes);