target/riscv: Print privilege level and ELP in riscv_cpu_dump_state
The privilege level and ELP are implicit state (like virt), so print them out. Signed-off-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260529053519.1224019-1-antonb@tenstorrent.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anton Blanchard committed
May 29, 2026 at 05:35 UTC
b3faeab53a9e2ea78e184fdeab23619d7ca7f318
1 file changed
+22
target/riscv/cpu.c
+22
@@ -577,6 +577,22 @@ static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f)
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}
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}
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+#if !defined(CONFIG_USER_ONLY)
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+static const char *riscv_priv_str(uint32_t priv)
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+{
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+ switch (priv) {
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+ case PRV_M:
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+ return "M";
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+ case PRV_S:
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+ return "S";
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+ case PRV_U:
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+ return "U";
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+ }
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+
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+ return "?";
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+}
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+#endif
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+
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static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
@@ -585,9 +601,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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uint8_t *p;
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#if !defined(CONFIG_USER_ONLY)
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+ qemu_fprintf(f, " %s %s\n", "priv = ", riscv_priv_str(env->priv));
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+
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
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}
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+
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+ if (cpu->cfg.ext_zicfilp) {
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+ qemu_fprintf(f, " %s %d\n", "elp = ", env->elp);
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+ }
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#endif
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qemu_fprintf(f, " %s %" PRIx64 "\n", "pc ", env->pc);
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#ifndef CONFIG_USER_ONLY