@samitouri / QOSamiQemu / commits / b439ffbb1b

target/riscv: Fix size of mseccfg

mseccfg is defined in version 20250508 of the privileged specification to be 64 bits in size. Update relevant function arguments. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260520125406.28693-22-anjo@rev.ng> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Anton Johansson committed May 20, 2026 at 14:53 UTC b439ffbb1bae4bb45008daf45b93dd490893987c

4 files changed +6 -6

target/riscv/cpu.h

+1 -1

@@ -465,7 +465,7 @@ struct CPUArchState {

465

466 /* physical memory protection */

467 pmp_table_t pmp_state;

468 - target_ulong mseccfg;

468 + uint64_t mseccfg;

469

470 /* trigger module */

471 uint16_t mcontext;

target/riscv/machine.c

+1 -1

@@ -439,7 +439,7 @@ static const VMStateDescription vmstate_mseccfg = {

439 .minimum_version_id = 1,

440 .needed = mseccfg_needed,

441 .fields = (const VMStateField[]) {

442 - VMSTATE_UINTTL(env.mseccfg, RISCVCPU),

442 + VMSTATE_UINT64(env.mseccfg, RISCVCPU),

443 VMSTATE_END_OF_LIST()

444 }

445 };

target/riscv/pmp.c

+2 -2

@@ -667,7 +667,7 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)

667 /*

668 * Handle a write to a mseccfg CSR

669 */

670 -void mseccfg_csr_write(CPURISCVState *env, target_ulong val)

670 +void mseccfg_csr_write(CPURISCVState *env, uint64_t val)

671 {

672 int i;

673 uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;

@@ -713,7 +713,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)

713 /*

714 * Handle a read from a mseccfg CSR

715 */

716 -target_ulong mseccfg_csr_read(CPURISCVState *env)

716 +uint64_t mseccfg_csr_read(CPURISCVState *env)

717 {

718 trace_mseccfg_csr_read(env->mhartid, env->mseccfg);

719 return env->mseccfg;

target/riscv/pmp.h

+2 -2

@@ -71,8 +71,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,

71 target_ulong val);

72 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);

74 -void mseccfg_csr_write(CPURISCVState *env, target_ulong val);

75 -target_ulong mseccfg_csr_read(CPURISCVState *env);

74 +void mseccfg_csr_write(CPURISCVState *env, uint64_t val);

75 +uint64_t mseccfg_csr_read(CPURISCVState *env);

77 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,

78 target_ulong val);