target/mips: decode Octeon ZUC and SNOW3G COP2 selectors
Add explicit decodetree entries and translator bindings for the Octeon ZUC and SNOW3G COP2 operation selectors. These stream-cipher selectors operate on the shared HSH register window state, so dispatch them through the per-operation helpers added with the corresponding engine support. Keep stream-cipher decode separate because these selectors share the HSH register window with unrelated engines. Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-17-daef7a0d8b04@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
James Hilliard committed
Jun 8, 2026 at 12:59 UTC
b6ed5076a39421b65761c04b2d9cbfac594ac004
2 files changed
+8
target/mips/tcg/octeon.decode
+4
@@ -265,8 +265,12 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx
265
CVM_MT_CRC_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 0111 &cp2
266
CVM_MT_CRC_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 1000 &cp2
267
CVM_MT_HSH_STARTMD5 010010 00101 rt:5 0100 0000 0100 0111 &cp2
268
+ CVM_MT_SNOW3G_START 010010 00101 rt:5 0100 0000 0100 1101 &cp2
269
+ CVM_MT_SNOW3G_MORE 010010 00101 rt:5 0100 0000 0100 1110 &cp2
270
CVM_MT_HSH_STARTSHA256 010010 00101 rt:5 0100 0000 0100 1111 &cp2
271
CVM_MT_SHA3_STARTOP 010010 00101 rt:5 0100 0000 0101 0010 &cp2
272
+ CVM_MT_ZUC_START 010010 00101 rt:5 0100 0000 0101 0101 &cp2
273
+ CVM_MT_ZUC_MORE 010010 00101 rt:5 0100 0000 0101 0110 &cp2
274
CVM_MT_HSH_STARTSHA 010010 00101 rt:5 0100 0000 0101 0111 &cp2
275
CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 1101 &cp2
276
CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 0000 &cp2
target/mips/tcg/octeon_translate.c
+4
@@ -345,6 +345,10 @@ CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT15, sha3_dat[15]);
345
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT16, sha3_dat[16]);
346
CP2_MT_XOR_I64(CVM_MT_SHA3_XORDAT17, sha3_dat[17]);
347
CP2_MT_HELPER_ENV(CVM_MT_SHA3_STARTOP, sha3_startop);
348
+CP2_MT_HELPER(CVM_MT_ZUC_START, zuc_start);
349
+CP2_MT_HELPER(CVM_MT_ZUC_MORE, zuc_more);
350
+CP2_MT_HELPER(CVM_MT_SNOW3G_START, snow3g_start);
351
+CP2_MT_HELPER(CVM_MT_SNOW3G_MORE, snow3g_more);
352
CP2_MT_HELPER(CVM_MT_HSH_STARTSHA1_COMPAT, hsh_startsha1_compat);
353
CP2_MT_I64(CVM_MT_HSH_DATW0, hsh_dat[0]);
354
CP2_MT_I64(CVM_MT_HSH_DATW1, hsh_dat[1]);