@samitouri / QOSamiQemu / commits / b7d87fb10d

hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL

When software clears CMD_ILL or CQMF error bits by writing 1 to CQCSR, the IOMMU should re-check the command queue and continue processing pending commands if head != tail. Per RISC-V IOMMU specification : If command-queue access leads to a memory fault then the command-queue-memory-fault bit is set to 1 and the commandqueue stalls until this bit is cleared. To re-enable command processing, software should clear this bit by writing 1. Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Message-ID: <20260518070143.8405-1-jay.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Jay Chang committed May 18, 2026 at 15:01 UTC b7d87fb10d53a918e9c4a3dfe1fb06ce42c52526
1 file changed +10
hw/riscv/riscv-iommu.c
+10
@@ -2034,6 +2034,16 @@ static void riscv_iommu_process_cq_control(RISCVIOMMUState *s)
2034 }
2035
2036 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, ctrl_set, ctrl_clr);
2037 +
2038 + /*
2039 + * After clearing error bits (CMD_ILL, CQMF), if queue is still active,
2040 + * re-process pending command.
2041 + */
2042 + ctrl_set = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_CQCSR);
2043 + if ((ctrl_set & RISCV_IOMMU_CQCSR_CQON) &&
2044 + !(ctrl_set & (RISCV_IOMMU_CQCSR_CMD_ILL | RISCV_IOMMU_CQCSR_CQMF))) {
2045 + riscv_iommu_process_cq_tail(s);
2046 + }
2047 }
2048
2049 static void riscv_iommu_process_fq_control(RISCVIOMMUState *s)