@samitouri / QOSamiQemu / commits / b9528999b3

hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff

A DMA transfer to destination address `0xffffffff` should trigger a bitstream load via the PCAP interface. Currently, this case is not intercepted, causing loaders to enter an infinite loop when polling the status register. This commit adds a check for `0xffffffff` as the destination address. If detected, the relevant status register bits (`DMA_DONE`, `DMA_P_DONE`, and `PCFG_DONE`) are set to indicate a successful bitstream load. If the address is different, the DMA transfer proceeds as usual. A successful load is indicated but nothing is actually done. Guests relying on FPGA functions are still known to fail. This feature is required for the integration of the Beckhoff CX7200 model. Signed-off-by: YannickV <Y.Vossen@beckhoff.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20260518073401.11279-2-corvin.koehne@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

YannickV committed May 18, 2026 at 09:33 UTC b9528999b34cdb0bfba013cb6452bdc43d862709

1 file changed +8 -1

hw/dma/xlnx-zynq-devcfg.c

+8 -1

@@ -247,7 +247,14 @@ static uint64_t r_lock_pre_write(RegisterInfo *reg, uint64_t val)

247 static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val)

248 {

249 XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);

250 -

250 + if ((s->regs[R_DMA_DST_ADDR]) == 0xffffffff) {

251 + DB_PRINT("bitstream loading detected\n");

252 + s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |

253 + R_INT_STS_DMA_P_DONE_MASK |

254 + R_INT_STS_PCFG_DONE_MASK;

255 + xlnx_zynq_devcfg_update_ixr(s);

256 + return;

257 + }

258 s->dma_cmd_fifo[s->dma_cmd_fifo_num] = (XlnxZynqDevcfgDMACmd) {

259 .src_addr = s->regs[R_DMA_SRC_ADDR] & ~0x3UL,

260 .dest_addr = s->regs[R_DMA_DST_ADDR] & ~0x3UL,