hw/riscv, target/riscv: move pmu fdt function to fdt-common.c
riscv_pmu_generate_fdt_node() can be moved to fdt_common.c since it has no PMU TCG internals. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Message-ID: <20260703180538.3346781-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 3, 2026 at 15:05 UTC
ba0b4e84aee186b5805f37bbd0abfee51193de79
5 files changed
+53
-54
hw/riscv/fdt-common.c
+52
@@ -230,3 +230,55 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size,
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}
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
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}
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+
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+/*
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+ * To keep it simple, any event can be mapped to any programmable counters in
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+ * QEMU. The generic cycle & instruction count events can also be monitored
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+ * using programmable counters. In that case, mcycle & minstret must continue
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+ * to provide the correct value as well. Heterogeneous PMU per hart is not
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+ * supported yet. Thus, number of counters are same across all harts.
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+ */
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+void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name)
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+{
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+ uint32_t fdt_event_ctr_map[15] = {};
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+
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+ /*
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+ * The event encoding is specified in the SBI specification
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+ * Event idx is a 20bits wide number encoded as follows:
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+ * event_idx[19:16] = type
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+ * event_idx[15:0] = code
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+ * The code field in cache events are encoded as follows:
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+ * event_idx.code[15:3] = cache_id
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+ * event_idx.code[2:1] = op_id
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+ * event_idx.code[0:0] = result_id
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+ */
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+
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+ /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */
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+ fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);
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+ fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);
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+ fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);
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+
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+ /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */
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+ fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);
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+ fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
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+ fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
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+
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+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
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+ fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
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+ fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
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+ fdt_event_ctr_map[8] = cpu_to_be32(cmask);
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+
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+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
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+ fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
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+ fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
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+ fdt_event_ctr_map[11] = cpu_to_be32(cmask);
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+
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+ /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
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+ fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
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+ fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
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+ fdt_event_ctr_map[14] = cpu_to_be32(cmask);
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+
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+ /* This a OpenSBI specific DT property documented in OpenSBI docs */
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+ qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters",
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+ fdt_event_ctr_map, sizeof(fdt_event_ctr_map));
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+}
hw/riscv/tt_atlantis.c
-1
@@ -17,7 +17,6 @@
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#include "hw/core/sysbus.h"
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#include "target/riscv/cpu.h"
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-#include "target/riscv/pmu.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/fdt-common.h"
hw/riscv/virt.c
-1
@@ -30,7 +30,6 @@
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#include "hw/char/serial-mm.h"
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#include "target/riscv/cpu.h"
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#include "hw/core/sysbus-fdt.h"
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-#include "target/riscv/pmu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/iommu.h"
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#include "hw/riscv/riscv-iommu-bits.h"
include/hw/riscv/fdt-common.h
+1
@@ -35,4 +35,5 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t size,
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uint32_t addr_cells, uint32_t *plic_cells,
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uint32_t cells_size, uint32_t ndev_sources,
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bool numa_enabled, int socket);
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+void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
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#endif
target/riscv/pmu.c
-52
@@ -27,58 +27,6 @@
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#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
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-/*
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- * To keep it simple, any event can be mapped to any programmable counters in
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- * QEMU. The generic cycle & instruction count events can also be monitored
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- * using programmable counters. In that case, mcycle & minstret must continue
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- * to provide the correct value as well. Heterogeneous PMU per hart is not
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- * supported yet. Thus, number of counters are same across all harts.
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- */
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-void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name)
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-{
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- uint32_t fdt_event_ctr_map[15] = {};
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-
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- /*
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- * The event encoding is specified in the SBI specification
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- * Event idx is a 20bits wide number encoded as follows:
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- * event_idx[19:16] = type
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- * event_idx[15:0] = code
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- * The code field in cache events are encoded as follows:
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- * event_idx.code[15:3] = cache_id
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- * event_idx.code[2:1] = op_id
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- * event_idx.code[0:0] = result_id
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- */
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-
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- /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */
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- fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);
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- fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);
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- fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);
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-
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- /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */
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- fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);
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- fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
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- fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
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-
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- /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
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- fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
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- fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
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- fdt_event_ctr_map[8] = cpu_to_be32(cmask);
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-
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- /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
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- fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
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- fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
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- fdt_event_ctr_map[11] = cpu_to_be32(cmask);
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-
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- /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
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- fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
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- fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
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- fdt_event_ctr_map[14] = cpu_to_be32(cmask);
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-
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- /* This a OpenSBI specific DT property documented in OpenSBI docs */
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- qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters",
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- fdt_event_ctr_map, sizeof(fdt_event_ctr_map));
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-}
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-
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static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
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{
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if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||