hw/misc/aspeed_hace: Enable the crypto command on the AST2700
With direct/scatter-gather access, 64-bit DMA and AES-GCM all in place, the AST2700 crypto engine is now fully modelled. Drop its temporary interrupt-only workaround so the crypto command runs for real, like the other HACE variants. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20260811060115.1849266-16-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Jamin Lin committed
Aug 11, 2026 at 06:01 UTC
baf15a2cf21c75ec9c3f068991cf28844887bf74
2 files changed
+1
-15
hw/misc/aspeed_hace.c
+1
-14
@@ -1005,14 +1005,7 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
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break;
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}
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case R_CRYPT_CMD:
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- /*
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- * The AST2700 crypto engine needs 64-bit DMA and AES-GCM, which are
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- * added later; until then it keeps the temporary workaround of only
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- * raising the completion interrupt without running the command.
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- */
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- if (!ahc->raise_crypt_interrupt_workaround) {
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- do_crypt_operation(s, data);
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- }
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+ do_crypt_operation(s, data);
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/* Hardware raises the crypt interrupt once the command finishes. */
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s->regs[R_STATUS] |= CRYPT_IRQ;
@@ -1214,12 +1207,6 @@ static void aspeed_ast2700_hace_class_init(ObjectClass *klass, const void *data)
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ahc->dest_hi_mask = 0x00000003;
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ahc->key_hi_mask = 0x00000003;
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- /*
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- * Currently, it does not support the CRYPT command. Instead, it only
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- * sends an interrupt to notify the firmware that the crypt command
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- * has completed. It is a temporary workaround.
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- */
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- ahc->raise_crypt_interrupt_workaround = true;
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ahc->has_dma64 = true;
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}
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include/hw/misc/aspeed_hace.h
-1
@@ -49,7 +49,6 @@ struct AspeedHACEClass {
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uint32_t key_mask;
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uint32_t hash_mask;
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uint64_t nr_regs;
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- bool raise_crypt_interrupt_workaround;
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uint32_t src_hi_mask;
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uint32_t dest_hi_mask;
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uint32_t key_hi_mask;