target/arm: add TCSO bitmasks to SCTLR
These are the bitmasks used to control the FEAT_MTE_STORE_ONLY feature. They are now named and setting these fields of SCTLR is ignored if MTE or MTE4 is disabled, as per convention. Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260529-feat-mte4-v7-2-ccbd3c14eb3c@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gabriel Brookman committed
May 29, 2026 at 12:52 UTC
bb5c28962fdb18b225e018fa6aae61c3c6644112
3 files changed
+21
-6
target/arm/cpu-features.h
+5
@@ -1196,6 +1196,11 @@ static inline bool isar_feature_aa64_mteperm(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTEPERM) >= 1;
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}
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+static inline bool isar_feature_aa64_mte_store_only(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTESTOREONLY) == 1;
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+}
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+
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static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0;
target/arm/cpu.h
+2
@@ -1468,6 +1468,8 @@ void pmu_init(ARMCPU *cpu);
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#define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
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#define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
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#define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
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+#define SCTLR_TCSO0 (1ULL << 58) /* FEAT_MTE_STORE_ONLY */
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+#define SCTLR_TCSO (1ULL << 59) /* FEAT_MTE_STORE_ONLY */
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#define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
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#define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
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#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
target/arm/helper.c
+14
-6
@@ -3300,12 +3300,20 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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/* ??? Lots of these bits are not implemented. */
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- if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
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- if (ri->opc1 == 6) { /* SCTLR_EL3 */
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- value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
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- } else {
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- value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
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- SCTLR_ATA0 | SCTLR_ATA);
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+ if (ri->state == ARM_CP_STATE_AA64) {
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+ if (!cpu_isar_feature(aa64_mte, cpu)) {
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+ if (ri->opc1 == 6) { /* SCTLR_EL3 */
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+ value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA | SCTLR_TCSO);
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+ } else {
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+ value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
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+ SCTLR_ATA0 | SCTLR_ATA | SCTLR_TCSO | SCTLR_TCSO0);
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+ }
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+ } else if (!cpu_isar_feature(aa64_mte_store_only, cpu)) { /* not mte4 */
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+ if (ri->opc1 == 6) { /* SCTLR_EL3 */
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+ value &= ~SCTLR_TCSO;
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+ } else {
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+ value &= ~(SCTLR_TCSO | SCTLR_TCSO0);
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+ }
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}
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}
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