@samitouri / QOSamiQemu / commits / bc02288cf1

target/arm: Define 'max' CPU type in cpu-max.c

Rather than having the 32-bit 'max' CPU type defined in cpu32.c and the 64-bit counter part in cpu64.c, unify the code in a single place in cpu-max.c. Define stubs for aarch64_host_initfn() and aarch64_max_tcg_initfn() in the 32-bit binary. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260526203722.79463-16-philmd@linaro.org>

Philippe Mathieu-Daudé committed May 15, 2026 at 09:27 UTC bc02288cf1568749d983deceb23d581b3c58c95c
5 files changed +77 -49
target/arm/cpu-max.c
+65
@@ -8,7 +8,10 @@
8
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 +#include "system/hw_accel.h"
12 #include "system/kvm.h"
13 +#include "system/qtest.h"
14 +#include "system/tcg.h"
15 #include "target/arm/internals.h"
16 #include "target/arm/cpregs.h"
17
@@ -178,3 +181,65 @@ void aa32_max_features(ARMCPU *cpu)
181
182 FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
183 }
184 +
185 +/*
186 + * -cpu max: a CPU with as many features enabled as our emulation supports.
187 + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
188 + * this only needs to handle 32 bits, and need not care about KVM.
189 + */
190 +static void cpu_max_initfn(Object *obj)
191 +{
192 + ARMCPU *cpu = ARM_CPU(obj);
193 +
194 +#ifdef TARGET_AARCH64
195 + const bool aarch64_enabled = true;
196 +#else
197 + const bool aarch64_enabled = false;
198 +#endif /* !TARGET_AARCH64 */
199 +
200 + if (hwaccel_enabled()) {
201 + assert(aarch64_enabled);
202 + /*
203 + * When hardware acceleration enabled, '-cpu max' is
204 + * identical to '-cpu host'
205 + */
206 + aarch64_host_initfn(obj);
207 + return;
208 + }
209 +
210 + if (tcg_enabled() || qtest_enabled()) {
211 + aarch64_aa32_a57_init(obj, !aarch64_enabled);
212 + }
213 +
214 + if (!aarch64_enabled) {
215 + aa32_max_features(cpu);
216 +#ifdef CONFIG_USER_ONLY
217 + /*
218 + * Break with true ARMv8 and add back old-style VFP short-vector
219 + * support. Only do this for user-mode, where -cpu max is the default,
220 + * so that older v6 and v7 programs are more likely to work without
221 + * adjustment.
222 + */
223 + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
224 +#endif
225 + } else if (tcg_enabled()) {
226 + assert(aarch64_enabled);
227 + /*
228 + * '-cpu max' for TCG: we currently do this as
229 + * "A57 with extra things"
230 + */
231 + aarch64_max_tcg_initfn(obj);
232 + }
233 +}
234 +
235 +static const ARMCPUInfo arm_max_cpu = {
236 + .name = "max",
237 + .initfn = cpu_max_initfn,
238 +};
239 +
240 +static void arm_max_cpu_register_types(void)
241 +{
242 + arm_cpu_register(&arm_max_cpu);
243 +}
244 +
245 +type_init(arm_max_cpu_register_types)
target/arm/cpu64.c
+1 -20
@@ -791,7 +791,7 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu)
791 }
792 #endif
793
794 -static void aarch64_host_initfn(Object *obj)
794 +void aarch64_host_initfn(Object *obj)
795 {
796 ARMCPU *cpu = ARM_CPU(obj);
797
@@ -818,28 +818,9 @@ static void aarch64_host_initfn(Object *obj)
818 }
819 }
820
821 -static void aarch64_max_initfn(Object *obj)
822 -{
823 - if (hwaccel_enabled()) {
824 - /* When hardware acceleration enabled, '-cpu max' is identical to '-cpu host' */
825 - aarch64_host_initfn(obj);
826 - return;
827 - }
828 -
829 - if (tcg_enabled() || qtest_enabled()) {
830 - aarch64_aa32_a57_init(obj, false);
831 - }
832 -
833 - /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
834 - if (tcg_enabled()) {
835 - aarch64_max_tcg_initfn(obj);
836 - }
837 -}
838 -
821 static const ARMCPUInfo aarch64_cpus[] = {
822 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
823 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
842 - { .name = "max", .initfn = aarch64_max_initfn },
824 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX)
825 { .name = "host", .initfn = aarch64_host_initfn },
826 #endif
target/arm/internals.h
+1
@@ -1774,6 +1774,7 @@ void aarch64_add_pauth_properties(Object *obj);
1774 void aarch64_add_sve_properties(Object *obj);
1775 void aarch64_add_sme_properties(Object *obj);
1776 void aarch64_aa32_a57_init(Object *obj, bool aa32_only);
1777 +void aarch64_host_initfn(Object *obj);
1778
1779 /* Return true if the gdbstub is presenting an AArch64 CPU */
1780 static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
target/arm/tcg/cpu32.c
-29
@@ -711,32 +711,6 @@ static void sa1110_initfn(Object *obj)
711 cpu->reset_sctlr = 0x00000070;
712 }
713
714 -#ifndef TARGET_AARCH64
715 -/*
716 - * -cpu max: a CPU with as many features enabled as our emulation supports.
717 - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
718 - * this only needs to handle 32 bits, and need not care about KVM.
719 - */
720 -static void arm_max_initfn(Object *obj)
721 -{
722 - ARMCPU *cpu = ARM_CPU(obj);
723 -
724 - /* Cortex-A57 advertising none of the aarch64 features */
725 - aarch64_aa32_a57_init(obj, true);
726 -
727 - aa32_max_features(cpu);
728 -
729 -#ifdef CONFIG_USER_ONLY
730 - /*
731 - * Break with true ARMv8 and add back old-style VFP short-vector support.
732 - * Only do this for user-mode, where -cpu max is the default, so that
733 - * older v6 and v7 programs are more likely to work without adjustment.
734 - */
735 - cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
736 -#endif
737 -}
738 -#endif /* !TARGET_AARCH64 */
739 -
714 static const ARMCPUInfo arm_tcg_cpus[] = {
715 { .name = "arm926", .initfn = arm926_initfn },
716 { .name = "arm946", .initfn = arm946_initfn },
@@ -760,9 +734,6 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
734 { .name = "ti925t", .initfn = ti925t_initfn },
735 { .name = "sa1100", .initfn = sa1100_initfn },
736 { .name = "sa1110", .initfn = sa1110_initfn },
763 -#ifndef TARGET_AARCH64
764 - { .name = "max", .initfn = arm_max_initfn },
765 -#endif
737 };
738
739 static void arm_tcg_cpu_register_types(void)
target/arm/tcg/stubs32.c
+10
@@ -22,3 +22,13 @@ void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
22 {
23 g_assert_not_reached();
24 }
25 +
26 +void aarch64_host_initfn(Object *obj)
27 +{
28 + g_assert_not_reached();
29 +}
30 +
31 +void aarch64_max_tcg_initfn(Object *obj)
32 +{
33 + g_assert_not_reached();
34 +}