target/arm: Implement FMMLA (FP8 to FP32) for AdvSIMD
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260609192110.752384-41-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson committed
Jun 9, 2026 at 12:21 UTC
bd61776fee728e14976e6ed13caabb5378ab4568
5 files changed
+35
target/arm/cpu-features.h
+5
@@ -1645,6 +1645,11 @@ static inline bool isar_feature_aa64_f8dp2(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8DP2);
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}
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+static inline bool isar_feature_aa64_f8mm8(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM8);
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+}
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+
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/*
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* Combinations of feature tests, for ease of use with TRANS_FEAT.
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*/
target/arm/tcg/a64.decode
+2
@@ -1227,6 +1227,8 @@ FMLALL_sb_v 0.00 1110 0.0 rm:5 110001 rn:5 rd:5 \
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FDOT_sb_v 0.00 1110 000 ..... 11111 1 ..... ..... @qrrr_s
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FDOT_hb_v 0.00 1110 010 ..... 11111 1 ..... ..... @qrrr_h
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+FMMLA_sb 0110 1110 100 ..... 11101 1 ..... ..... @rrr_q1e0
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+
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### Advanced SIMD scalar x indexed element
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FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
target/arm/tcg/fp8_helper.c
+25
@@ -807,3 +807,28 @@ void HELPER(gvec_fdot_idx_hb)(void *vd, void *vn, void *vm,
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clear_tail(vd, oprsz, simd_maxsz(desc));
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}
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+
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+void HELPER(gvec_fmmla_sb)(void *vd, void *vn, void *vm,
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+ CPUARMState *env, uint32_t desc)
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+{
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+ FP8MulContext ctx = fp8_mul_start(env, -1);
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+ size_t oprsz = simd_oprsz(desc);
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+ size_t nseg = oprsz / 16;
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+ uint64_t *n = vn;
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+ uint64_t *m = vm;
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+ float32 *d = vd;
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+
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+ for (size_t seg = 0; seg < nseg; seg++, d += 4, n += 2, m += 2) {
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+ float32 d0 = f8dotadd_s(n[0], m[0], 8, d[H4(0)], &ctx);
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+ float32 d1 = f8dotadd_s(n[0], m[1], 8, d[H4(1)], &ctx);
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+ float32 d2 = f8dotadd_s(n[1], m[0], 8, d[H4(2)], &ctx);
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+ float32 d3 = f8dotadd_s(n[1], m[1], 8, d[H4(3)], &ctx);
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+
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+ d[H4(0)] = d0;
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+ d[H4(1)] = d1;
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+ d[H4(2)] = d2;
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+ d[H4(3)] = d3;
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+ }
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+
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+ clear_tail(vd, oprsz, simd_maxsz(desc));
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+}
target/arm/tcg/helper-fp8-defs.h
+2
@@ -35,3 +35,5 @@ DEF_HELPER_FLAGS_5(gvec_fdot_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
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DEF_HELPER_FLAGS_5(gvec_fdot_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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DEF_HELPER_FLAGS_5(gvec_fdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
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+
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+DEF_HELPER_FLAGS_5(gvec_fmmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
target/arm/tcg/translate-a64.c
+1
@@ -7515,6 +7515,7 @@ static bool do_f8dot(DisasContext *s, arg_qrrr_e *a,
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TRANS_FEAT(FDOT_sb_v, aa64_f8dp4, do_f8dot, a, gen_helper_gvec_fdot_sb)
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TRANS_FEAT(FDOT_hb_v, aa64_f8dp2, do_f8dot, a, gen_helper_gvec_fdot_hb)
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+TRANS_FEAT(FMMLA_sb, aa64_f8mm8, do_f8dot, a, gen_helper_gvec_fmmla_sb)
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static bool do_f8dot_idx(DisasContext *s, arg_qrrx_e *a,
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gen_helper_gvec_3_ptr *fn)