target/riscv: move riscv_cpu_set_geilen() to riscv-imsic
riscv_imsic.c is the only caller. Having it sitting in the TCG only cpu_helper.c gets in the way of --disable-tcg for no good reason. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260703180538.3346781-23-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 3, 2026 at 15:05 UTC
beecb309582869e86ab1c38e3cfbf14ab18fe008
3 files changed
+13
-14
hw/intc/riscv_imsic.c
+13
@@ -46,6 +46,19 @@
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#define IMSIC_EISTATE_ENPEND (IMSIC_EISTATE_ENABLED | \
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IMSIC_EISTATE_PENDING)
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+static void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen)
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+{
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+ if (!riscv_has_ext(env, RVH)) {
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+ return;
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+ }
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+
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+ if (geilen > (TARGET_LONG_BITS - 1)) {
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+ return;
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+ }
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+
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+ env->geilen = geilen;
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+}
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+
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static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
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{
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uint32_t i, max_irq, base;
target/riscv/cpu.h
-1
@@ -646,7 +646,6 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env,
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bool riscv_cpu_fp_enabled(CPURISCVState *env);
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-void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen);
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bool riscv_cpu_vector_enabled(CPURISCVState *env);
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void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
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int riscv_env_mmu_index(CPURISCVState *env, bool ifetch);
target/riscv/tcg/cpu_helper.c
-13
@@ -526,19 +526,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
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}
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}
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-void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen)
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-{
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- if (!riscv_has_ext(env, RVH)) {
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- return;
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- }
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-
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- if (geilen > (TARGET_LONG_BITS - 1)) {
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- return;
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- }
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-
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- env->geilen = geilen;
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-}
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-
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void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level)
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{
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CPURISCVState *env = &cpu->env;