hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN
We must check if IOHGATP_PPN is 16kb aligned for non-bare GATP modes. Fixes: 69a9ae4836 ("hw/riscv/riscv-iommu: add ATS support") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3550 Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Message-ID: <20260702203616.1795588-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
Jul 2, 2026 at 17:36 UTC
bf274c54295c81aeda3835e2e0bc971f0bd57f47
1 file changed
+15
hw/riscv/riscv-iommu.c
+15
@@ -862,6 +862,21 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMUState *s,
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return false;
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}
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+ if (gatp != RISCV_IOMMU_DC_IOHGATP_MODE_BARE) {
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+ uint64_t iohgatp_ppn = get_field(ctx->gatp,
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+ RISCV_IOMMU_DC_IOHGATP_PPN);
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+
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+ /*
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+ * One of the conditions for a misconfigured DDT entry
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+ * according to the riscv-spec: "DC.iohgatp.MODE is not
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+ * Bare and the root page table (address) determined by
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+ * DC.iohgatp.PPN is not aligned to a 16-KiB boundary."
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+ */
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+ if (PPN_PHYS(iohgatp_ppn) & ((1ULL << 14) - 1)) {
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+ return false;
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+ }
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+ }
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+
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fsc_mode = get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE);
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if (ctx->tc & RISCV_IOMMU_DC_TC_PDTV) {