@samitouri / QOSamiQemu / commits / bf6530630e

target/arm/hvf: seed NO_RAW ID registers from isar.idregs[] on vCPU init

Commit 887eaa8a29 ("target/arm: implement FEAT_RNG_TRAP for RNDR/RNDRRS") gave ID_AA64ISAR0_EL1 a readfn so the RNDR field can reflect SCR_EL3.TRNDR at read time, and marked the cpreg ARM_CP_NO_RAW in the system-emulation path. HVF then trips its hvf_arch_init_vcpu() assertion that no ID register in hvf_sreg_list[] is NO_RAW, aborting on boot on Apple Silicon: Assertion failed: (!(ri->type & ARM_CP_NO_RAW)), function hvf_arch_init_vcpu, file hvf.c, line 1441. Reproduce with: qemu-system-aarch64 -M virt,accel=hvf -cpu host \ -nographic -display none -bios /dev/null Fix it the same way ID_AA64PFR0_EL1 already is: list HV_SYS_REG_ID_AA64ISAR0_EL1 in the SYNC_NO_RAW_REGS block in sysreg.c.inc so the assert loop skips it, and seed the vCPU's copy at init time. While here, unify how the three isar.idregs[]-backed ID registers are seeded. isar.idregs[] already holds QEMU's intended value for each (the host caps, probed once at realize via hv_vcpu_config_get_feature_reg(), plus any QEMU adjustment), so there is no need to read each register back from the vCPU first. Seed PFR0, ISAR0 and MMFR0 directly from isar.idregs[], dropping the two per-vCPU hv_vcpu_get_sys_reg() reads: - PFR0: take the GIC sysreg-interface bit from env->gicv3state, as the id_aa64pfr0_read() readfn does. Identical to the previous code whenever a GICv3 sysreg interface is present (the configuration HVF runs in practice); it differs only in that a vCPU with no GICv3 now reports ID_AA64PFR0_EL1.GIC == 0 instead of inheriting the host's value, which matches the field's meaning. - ISAR0: no overlay is needed; HVF does not expose EL3, so SCR_EL3.TRNDR is never set and the readfn is constant. - MMFR0: still clamp PARANGE to the chosen IPA size, updating isar.idregs[] in place because the page-table walker and the ID_AA64MMFR0_EL1 cpreg resetvalue read PARANGE back from there. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3533 Reported-by: Zenghui Yu <zenghui.yu@linux.dev> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Fixes: 887eaa8a29 ("target/arm: implement FEAT_RNG_TRAP for RNDR/RNDRRS") Signed-off-by: Jason Wright <wrigjl@proton.me> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Zenghui Yu <zenghui.yu@linux.dev> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Jason Wright committed Jun 29, 2026 at 20:52 UTC bf6530630e8c997b812e902638ec046b2274649f

2 files changed +5 -7

target/arm/hvf/hvf.c

+4 -6

@@ -1478,20 +1478,18 @@ int hvf_arch_init_vcpu(CPUState *cpu)

1478 arm_cpu->mp_affinity);

1479 assert_hvf_ok(ret);

1480

1481 - ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);

1482 - assert_hvf_ok(ret);

1481 + pfr = GET_IDREG(&arm_cpu->isar, ID_AA64PFR0);

1482 pfr |= env->gicv3state ? (1 << 24) : 0;

1483 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);

1484 assert_hvf_ok(ret);

1485

1487 - /* We're limited to underlying hardware caps, override internal versions */

1488 - ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,

1489 - &arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]);

1486 + ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64ISAR0_EL1,

1487 + GET_IDREG(&arm_cpu->isar, ID_AA64ISAR0));

1488 assert_hvf_ok(ret);

1489

1490 clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar);

1491 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,

1494 - arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]);

1492 + GET_IDREG(&arm_cpu->isar, ID_AA64MMFR0));

1493 assert_hvf_ok(ret);

1494

1495 if (!hvf_irqchip_in_kernel()) {

target/arm/hvf/sysreg.c.inc

+1 -1

@@ -89,13 +89,13 @@ DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 2, 0, 0, 2, 0)

89 DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 3, 0, 0, 0, 0)

90 DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 3, 0, 0, 0, 5)

91 DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)

92 +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)

93 #endif

95 DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)

96 /* Add ID_AA64PFR2_EL1 here when HVF supports it */

97 DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)

98 DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)

98 -DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)

99 DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)

100

101 #ifdef SYNC_NO_MMFR0